SC667201MMG3 datasheet(71/120 Pages) FREESCALE

71 / 120 page

MPC5642A Microcontroller Data Sheet, Rev. 3.1

Freescale Semiconductor

Electrical characteristics

RPUPD100K

C Weak pull-up/down

resistance21, 100 k



option

—

140



RPUPD5K

C Weak pull-up/down

resistance21, 5 k

 option

5 V ± 10% supply

1.4

—

5.2



3.3 V ± 10% supply

1.7

—

7.7

RPUPD5K

SR C

Weak Pull-Up/Down

Resistance21,

 Option

5 V ± 5% supply

1.4

—

7.5



RPUPDMTCH

C Pull-up/Down

Resistance matching

ratios (100K/200K)

Pull-up and

pull-down

resistances both

enabled and

settings are equal.

–2.5

—

2.5

TA (TL to TH)

P Operating temperature

range - ambient

(packaged)

—

–40.0

—

125.0

°C

—

D Slew rate on power supply

pins

——

—

V/ms

1 These specifications are design targets and subject to change per device characterization.

2 These specifications apply when V

RC33 is supplied externally, after disabling the internal regulator (VDDREG =0).

3 ADC is functional with 4 V

 V

DDA  4.75 V but with derated accuracy. This means the ADC will continue to function

at full speed with no undesirable behavior, but the accuracy will be degraded.

4 The V

DDF supply is connected to VDD in the package substrate. This specification applies to calibration package

devices only.

5 V

FLASH is available in the calibration package only.

6 Regulator is functional, with derated performance, with supply voltage down to 4.0 V

7 Multi-voltage power supply cannot be below 4.5 V when in low-swing mode

8 The slew rate (SRC) setting must be 0b11 when in low-swing mode.

9 While in low-swing mode there are no restrictions in transitioning to high-swing mode.

10 Pin in low-swing mode can accept a 5 V input

11 All V

OL/VOH values 100% tested with ± 2 mA load except where otherwise noted

12 Bypass mode, system clock @ 1 MHz (using system clock divider), PLL shut down, CPU running simple executive

code, 4 x ADC conversion every 10 ms, 2 x PWM channels @ 1 kHz, all other modules stopped.

13 Bypass mode, system clock @ 1 MHz (using system clock divider), CPU stopped, PIT running, all other modules

stopped

14 If 1.2V and 3.3V internal regulators are on,then iddreg=70mA

If supply is external that is 3.3V internal regulator is off, then iddreg=15mA

15 Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on

a particular I/O segment, and the voltage of the I/O segment. See Table 21 for values to calculate power dissipation

for specific operation. The total power consumption of an I/O segment is the sum of the individual power

consumptions for each pin on the segment.

16 Absolute value of current, measured at V

IL and VIH

17 Weak pull-up/down inactive. Measured at V

DDE = 3.6 V and VDDEH = 5.25 V. Applies to all digital pad types.

Table 20. DC electrical specifications1 (continued)

Symbol

Parameter

Conditions

Value

Unit

Min

Typ

Max

SC667201MMG3 Arkusz danych(PDF) 71 Page - Freescale Semiconductor, Inc

SC667201MMG3 Arkusz danych(HTML) 71 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Arkusz danych Pobierz

Link URL