SC667201MMG3 datasheet(9/120 Pages) FREESCALE

9 / 120 page

MPC5642A Microcontroller Data Sheet, Rev. 3.1

Freescale Semiconductor

Introduction

1.5

Feature details

1.5.1

e200z4 core

MPC5642A devices have a high performance e200z4 core processor:

•

32-bit Power Architecture technology programmer’s model

•

Variable Length Encoding (VLE) enhancements

•

Dual issue, 32-bit Power Architecture technology compliant CPU

•

8 KB, 2/4-way set associative instruction cache

•

Thirty-two 64-bit general purpose registers (GPRs)

•

Memory Management Unit (MMU) with 24-entry fully-associative translation look-aside buffer (TLB)

•

Harvard Architecture: Separate instruction bus and load/store bus

•

Vectored interrupt support

•

Non-maskable interrupt input

•

Critical Interrupt input

•

New ‘Wait for Interrupt’ instruction, to be used with new low power modes

•

Reservation instructions for implementing read-modify-write accesses

•

Signal processing extension (SPE) APU

•

Single Precision Floating point (scalar and vector)

•

Nexus Class 3+ debug

•

Process ID manipulation for the MMU using an external tool

•

In-order execution and retirement

•

Precise exception handling

•

Branch processing unit

— Dedicated branch address calculation adder

— Branch target prefetching using 8-entry BTB

•

Supports independent instruction and data accesses to different memory subsystems, such as SRAM and flash memory

via independent Instruction and Data BIUs

•

Load/store unit

— 2-cycle load latency

— Fully pipelined

— Big and Little endian support

— Misaligned access support

•

Signal Processing Extension (SPE1.1) APU supporting SIMD fixed-point operations using the 64-bit General Purpose

•

Embedded Floating-Point (EFP2) APU supporting scalar and vector SIMD single-precision floating-point operations,

using the 64-bit General Purpose Register file

•

Power management

— Low power design – extensive clock gating

— Power saving modes: wait

— Dynamic power management of execution units, cache and MMU

•

Testability

— Synthesizeable, MuxD scan design

— ABIST/MBIST for arrays

— Built-in Parallel Signature Unit

SC667201MMG3 Arkusz danych(PDF) 9 Page - Freescale Semiconductor, Inc

SC667201MMG3 Arkusz danych(HTML) 9 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Arkusz danych Pobierz

Link URL