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SC667201MMG3 Arkusz danych(PDF) 91 Page - Freescale Semiconductor, Inc |
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SC667201MMG3 Arkusz danych(HTML) 91 Page - Freescale Semiconductor, Inc |
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91 / 120 page ![]() MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 91 Electrical characteristics 8tEVTOPW CC D EVTO Pulse Width 1 — tMCYC 9tTCYC CC D TCK Cycle Time 46,7 —tCYC 9a tTCYC CC D Absolute Minimum TCK Cycle Time 1008 —ns 10 tTDC CC D TCK Duty Cycle 40 60 % 11 tNTDIS CC D TDI Data Setup Time 10 — ns 12 tNTDIH CC D TDI Data Hold Time 25 — ns 13 tNTMSS CC D TMS Data Setup Time 10 — ns 14 tNTMSH CC D TMS Data Hold Time 25 — ns 15 — CC D TDO propagation delay from falling edge of TCK — 19.5 ns 16 — CC D TDO hold time wrt TCK falling edge (minimum TDO propagation delay) 5.25 — ns 1 All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified at VDD = 1.14 V to 1.32 V, VDDEH = 4.75 V to 5.25 V with multi-voltage pads programmed to Low-Swing mode, TA =TL to TH, and CL = 30 pF with DSC = 0b10. 2 Achieving the absolute minimum MCKO cycle time may require setting the MCKO divider to more than its minimum setting (NPC_PCR[MCKO_DIV] depending on the actual system frequency being used. 3 This is a functionally allowable feature. However, this may be limited by the maximum frequency specified by the Absolute minimum MCKO period specification. 4 This may require setting the MCO divider to more than its minimum setting (NPC_PCR[MCKO_DIV]) depending on the actual system frequency being used. 5 MDO, MSEO, and EVTO data is held valid until next MCKO low cycle. 6 Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the design (system frequency / 4) depending on the actual system frequency being used. 7 This is a functionally allowable feature. However, this may be limited by the maximum frequency specified by the Absolute minimum TCK period specification. 8 This may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the design (system frequency / 4) depending on the actual system frequency being used. Table 38. Nexus debug port timing1 (continued) # Symbol C Characteristic Value Unit Min Max |
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