SC667201MMG3 datasheet(79/120 Pages) FREESCALE

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MPC5642A Microcontroller Data Sheet, Rev. 3.1

Freescale Semiconductor

Electrical characteristics

3.13

Configuring SRAM wait states

Use the SWSC field in the ECSM_MUDCR register to specify an additional wait state for the device SRAM. By default, no

wait state is added.

Please see the device reference manual for details.

DIFFmax

Maximum

differential voltage

(DANx+ - DANx-) or

(DANx- - DANx+)5

PREGAIN

set to 1X

setting

—

(VRH - VRL)/2

DIFFmax2

PREGAIN

set to 2X

setting

—

(VRH - VRL)/4

DIFFmax4

PREGAIN

set to 4X

setting

—

(VRH - VRL)/8

DIFFcmv

Differential input

Common mode

voltage (DANx- +

DANx+)/25

—(VRH + VRL)/2 - 5% (VRH + VRL)/2 + 5%

1 Applies only to differential channels.

2 Variable gain is controlled by setting the PRE_GAIN bits in the ADC_ACR1-8 registers to select a gain factor of

1, 2, or 4.

Settings are for differential input only. Tested at

1 gain. Values for other settings are guaranteed by as indicated.

3 At V

RH – VRL = 5.12 V, one LSB = 1.25 mV.

4 Guaranteed 10-bit mono tonicity.

5 Voltages between VRL and VRH will not cause damage to the pins. However, they may not be converted accurately if the

differential voltage is above the maximum differential voltage. In addition, conversion errors may occur if the common mode

voltage of the differential signal violates the Differential Input common mode voltage specification.

Table 30. Cutoff frequency for additional SRAM wait state

1 Max frequencies including 2% PLL FM.

SWSC Value

153

Table 29. eQADC differential ended conversion specifications (operating) (continued)

Symbol

Parameter

Value

Unit

min

max

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