QG80331M800 datasheet(63/67 Pages) INTEL

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Specification Update

Intel® 80331 I/O Processor

Documentation Changes

SDCR0 and SDCR1 register updates

Problem:

The SDCR0 (Table 236) and SDCR1 (Table 237) register description needs to be updated.

Workaround:

Table 236.

DDR SDRAM Control Register 0 - SDCR0 (Sheet 1 of 2)

Bit

Default

Description

31:28

RAS: Active to Precharge duration in MCLK periods

Equation 7: RAS = tRAS - 1

where tRAS is from SPD

Reserved

26:24

0002

RP: Precharge Command Period in MCLK periods

Equation 8: RP = tRP - 1

where tRP is from SPD

Reserved

22:20

0002

RCD: Active to Read, Active to Write Period in MCLK periods

Equation 9: RCD = tRCD - 1

where tRCD is from SPD

19:18

002

Reserved

17:16

012

EDP: Data Path Latency in MCLK periods

This field should be programmed to 102.

15:14

002

Reserved

13:12

002

WDL: Write Data Latency in MCLK periods used by the Memory Controller state machine. See

Equation 11.

•

00 = 0 MCLK periods (tCAS = 2.5) - (DDR-I Type only)

•

01 = 1 MCLK period (tCAS = 3) - (DDR-II Type only) - not supported

•

10 = 2 MCLK periods (tCAS = 4) - (DDR-II Type only)

11 = reserved

where tCAS is from SPD

11:10

002

Reserved

09:08

002

CAS: CAS Latency: Indicates the CAS Latency used by the Memory Controller state machine.

Encoded value based on tCAS from SPD

•

00 = reserved

•

01 = 2.5 MCLK periods (DDR-I Type only)

•

10 = 3 MCLK periods (DDR-II Type only) - not supported

•

11 = 4 MCLK periods (DDR-II Type only)

PCI

IOP

Attributes

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

Intel XScale® core Local Bus Address

FFFF E504H

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