QG80331M800 datasheet(57/67 Pages) INTEL

57 / 67 page

Specification Update

Intel® 80331 I/O Processor

Specification Clarifications

22.

AAU result can be written directly to PCI host memory

Issue:

The Application Accelerator Unit (AAU) can write results not only to local memory but also to the

PCI bus host memory via the ATU.

This feature can be applied to degraded RAID-5 reads, where the AAU result is the reconstructed

data for the host I/O read. The AAU can write its result to PCI; therefore, the degraded read XOR

result can be written directly to host memory. This eliminates the need for a DMA operation to

transfer the result from local memory to host memory via PCI.

Savings for the RAID application include the following:

• No DMA descriptor needs to be generated.

• No DMA interrupt needs to be serviced.

• Memory and internal bus bandwidth is saved (result write by AAU and read by DMA).

• Read I/O is serviced faster (eliminates latency of DMA operation).

Note:

AAU source reads from PCI are not supported; only local memory can be used for this.

Status:

No Fix. See the Table , “Summary Table of Changes” on page 9.

23.

PWRDELAY functionality during power sequencing

Issue:

When the 3.3 V rail is powered on and the 1.5 V rail is powered off, the PWRDELAY input signal

drives out until the 1.5 V rail powers up. This is important to understand if still using the legacy

power-fail circuit, because it might cause other circuitry to function incorrectly. The proper usage

of PWRDELAY is described in specification change 11 (“PWRDELAY needs only a pull-up for

battery back-up mode”), which recommends that PWRDELAY be isolated from all circuitry and

tied to a 1.5 K pull-up resistor.

Status:

No Fix. See the Table , “Summary Table of Changes” on page 9.

24.

PBI lockout condition

Issue:

When the core is in a tight loop writing to the PBI bus, while the DMA is doing a large block

transfer (for example, from SRAM, located on the PBI, to DDR memory), the DMA can be locked

out of accessing the PBI and the transaction will never complete.

If this condition occurs, use one of these workarounds:

1. Change the MTTR1 from 98h (default) to a lower value (such as 01h). A lower value allows the

DMA (or ATU which can also master a transaction to the PBI) to gain access to the PBI, because

the BIU is given shorter access for back-to-back BIU internal bus transactions.

2. Add a core read along with the core write, causing it to stall and preventing it from starving the

DMA.

3. Add NOPs or dummy instructions to ensure the loop spans greater than two cache lines.

4. Modify the loop such that the write is not done on every iteration.

Status:

No Fix. See the Table , “Summary Table of Changes” on page 9.

25.

Interleaving descriptors with D-0 AAU

Issue:

The P+Q capability is enabled in the AAU globally (ACR.3), not on a descriptor by descriptor

basis.

QG80331M800 Arkusz danych(PDF) 57 Page - Intel Corporation

QG80331M800 Arkusz danych(HTML) 57 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

Arkusz danych Pobierz

Link URL