QG80331M800 datasheet(51/67 Pages) INTEL

51 / 67 page

Specification Update

Intel® 80331 I/O Processor

Specification Clarifications

64 MB and 2 GB DDR333 capacities not to be tested in post-silicon

validation

Issue:

Intel is not able to test 64 MB and 2 GB DDR333 DIMMs due to availability. Intel cannot

guarantee proper functionality since validation cannot be completed.

Status:

No Fix. See the Table , “Summary Table of Changes” on page 9.

DDR-II 400 Unbuffered DIMMs are not supported

Issue:

The Intel® 80331 I/O processor (80331) supports DDR333 buffered (registered) and unbuffered

DIMMs, but only supports DDR-II 400 buffered (registered) DIMMs. DDR-II 400 unbuffered

DIMMs are not supported.

Status:

No Fix. See the Table , “Summary Table of Changes” on page 9.

Interrupt behavior in the 80331 no bridge mode

Issue:

When in the 80331 No Bridge Mode (BRG_EN = 0), the external interrupts behave just like when

the bridge is enabled in the 80331 (BRG_EN = 1), in that the S_INT[D:A]# interrupt inputs can be

forwarded to the P_INT[D:A]# interrupt outputs. The only difference between the two modes is

how the internal Messaging Unit interrupt is forwarded. In the 80331 Mode, it is forwarded to

P_INTC#, and in the 80331 No Bridge Mode it is forwarded on P_INTA#.

Status:

No Fix. See the Table , “Summary Table of Changes” on page 9.

Memory map for 2 GByte of DDR memory

Issue:

The 80331 can support up to 2Gbytes of DDR SDRAM, but it cannot cross a 2GB boundary,

therefore it must be mapped to either 0x00000000 - 0x7fffffff or 0x80000000 - 0xffffffff. Either

range conflicts with one or more of the statically assigned regions. The recommendation is to

disable the direct outbound ATU window, in order to use the larger 2GB memory, by clearing

ATUCR.8 (default setting is ‘0’ - disabled).

Status:

No Fix. See the Table , “Summary Table of Changes” on page 9.

Back to back MCU MMR reads

Issue:

The memory controller unit (MCU) returns the wrong memory mapped register (MMR) read data,

when two MMR read transactions are enqueued into the transaction queues at the same time. This

cannot happen from the BIU port as mapping the MMRs to this space is illegal. The only way this

can occur is for two internal bus devices to request info from the MCU MMRs at the same time

(with different addresses). For example, the BIU (via the Intel XScale

® core) and the ATU (via the

host), which is a very unlikely usage model.

Status:

No Fix. See the Table , “Summary Table of Changes” on page 9.

QG80331M800 Arkusz danych(PDF) 51 Page - Intel Corporation

QG80331M800 Arkusz danych(HTML) 51 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

Arkusz danych Pobierz

Link URL