QG80331M800 datasheet(37/67 Pages) INTEL

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Specification Update

Intel® 80331 I/O Processor

Non-Core Errata

52.

Enabling the core-to-memory port can cause a stall condition

Problem:

A stall condition can occur during high data throughput to the Memory Controller Unit (MCU),

due to a non-empty Bus Interface Unit (BIU) data queue that might allow no further traffic to be

submitted from the Intel XScale

® core. The stall is due to an invalid state in the queue control

registers and the associated pointers. The pointers and the queue status bits get out of sync,

allowing part of the BIU to conclude that it is full and therefore not to accept any more

transactions. The other part of the BIU concludes that it is empty, and therefore does not flush the

non-empty condition.

The stall condition can be generated in the following scenario:

1. Within the MCU, accept a read from one port (core-to-memory or IB-MCU). This triggers an

automatic coherency check, which requires writes within the same 1 K address “page” to be

pushed ahead of the read.

2. An “incoherent” write (in other words, a write that must precede the read from step 1) must

exist in the opposite port. This write is executed to DDR memory as normal.

3. A read must also exist in the opposite port; destination (coherent or incoherent) is unimportant.

This has the effect of maintaining the port’s request to the MCU.

4. An incoherent write arrives in the original port during the exact cycle the opposite write is

completed.

5. Due to the combination of pending read request and last-second incoherent write, the MCU

gets out of sync and attempts to acknowledge a write from the wrong port. This causes the

offending queue pointer/status bit mismatch. This situation locks the opposite port to the

original read transaction.

Implication:

Enabling the core-to-memory port (BIUCR.0 = 1, IB address = FFFF_E608h) can cause a stall

condition or data corruption.

Workaround:

Do not enable the core-to-memory port in the BIU Control Register (BIUCR.0). When

BIUCR.0 = 0 (default condition), the core-to-memory port is disabled and forces all Intel XScale®

core memory transactions to be issued out the core internal bus (IB) port, therefore avoiding the

stall condition.

Note:

Disabling the core-to-memory port requires a review of specification clarification 13, “Bus

Interface Unit follows PCI ordering rules” on page 54.

Status:

Fixed. Fixed in D-0 stepping. See the Table , “Summary Table of Changes” on page 9.

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