LSM9DS0TR datasheet(41/74 Pages) STMICROELECTRONICS

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LSM9DS0

The device contains a set of registers which are used to control its behavior and to retrieve

angular rate data. The register address, consisting of 7 bits, is used to identify them and to

write the data through the serial interface.

8.1

WHO_AM_I_G (0Fh)

Device identification register.

8.2

CTRL_REG1_G (20h)

DR[1:0] is used for ODR selection. BW [1:0] is used for Bandwidth selection.

In Table 21 all frequencies resulting in combinations of DR / BW bits are given.

Table 18. WHO_AM_I_G register

11010100

Table 19. CTRL_REG1_G register

DR1

DR0

BW1

BW0

Zen

Xen

Yen

Table 20. CTRL_REG1_G description

DR1-DR0

Output data rate selection. Refer to Table 21

BW1-BW0

Bandwidth selection. Refer to Table 21

Power-down mode enable. Default value: 0

(0: power-down mode, 1: normal mode or sleep mode)

Zen

Z-axis enable. Default value: 1

(0: Z-axis disabled; 1: Z-axis enabled)

Yen

Y-axis enable. Default value: 1

(0: Y-axis disabled; 1: Y-axis enabled)

Xen

X-axis enable. Default value: 1

(0: X-axis disabled; 1: X-axis enabled)

Table 21. DR and BW configuration setting

DR [1:0]

BW [1:0]

ODR (Hz)

Cutoff

12.5

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