FDC2114 datasheet(21/61 Pages) TI1

21 / 61 page

FDC2212, FDC2214, FDC2112, FDC2114

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SNOSCZ5A – JUNE 2015 – REVISED JUNE 2015

Table 11. Input Deglitch Filter Register

MUX_CONFIG.DEGLITCH (addr 0x1B) REGISTER

CHANNEL(1)

DEGLITCH FREQUENCY

VALUE

ALL

001

1 MHz

ALL

100

3.3 MHz

ALL

101

10 MHz

ALL

011

33 MHz

(1)

Channels 2 and 3 are available for FDC2114 / FDC2214 only.

9.4 Device Functional Modes

9.4.1 Start-up Mode

When the FDC powers up, it enters into Sleep Mode and will wait for configuration. Once the device is

configured, exit Sleep Mode by setting CONFIG.SLEEP_MODE_EN to b0.

It is recommended to configure the FDC while in Sleep Mode. If a setting on the FDC needs to be changed,

return the device to Sleep Mode, change the appropriate register, and then exit Sleep Mode.

9.4.2 Normal (Conversion) Mode

When operating in the normal (conversion) mode, the FDC is periodically sampling the frequency of the

sensor(s) and generating sample outputs for the active channel(s).

9.4.3 Sleep Mode

Sleep Mode is entered by setting the CONFIG.SLEEP_MODE_EN register field to 1. While in this mode, the

After setting CONFIG.SLEEP_MODE_EN to b0, sensor activation for the first conversion will begin after 16,384

fINT clock cycles. While in Sleep Mode the I2C interface is functional so that register reads and writes can be

performed. While in Sleep Mode, no conversions are performed. In addition, entering Sleep Mode will clear any

error condition and de-assert the INTB pin.

9.4.4 Shutdown Mode

When the SD pin is set to high, the FDC will enter Shutdown Mode. Shutdown Mode is the lowest power state.

To exit Shutdown Mode, set the SD pin to low. Entering Shutdown Mode will return all registers to their default

state.

While in Shutdown Mode, no conversions are performed. In addition, entering Shutdown Mode will clear any

error condition and de-assert the INTB pin. While the device is in Shutdown Mode, is not possible to read to or

write from the device via the I2C interface.

9.4.4.1 Reset

The FDC can be reset by writing to RESET_DEV.RESET_DEV. Conversion will stop and all register values will

return to their default value. This register bit will always return 0b when read.

9.5 Programming

The FDC device uses an I2C interface to access control and data registers.

9.5.1 I2C Interface Specifications

The FDC uses an extended start sequence with I2C for register access. The maximum speed of the I2C

interface is 400 kbit/s. This sequence follows the standard I2C 7-bit slave address followed by an 8-bit pointer

ADDR pin is set high, the FDC I2C address is 0x2B. The ADDR pin must not change state after the FDC exits

Shutdown Mode.

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