FDC2114 datasheet(35/61 Pages) TI1

35 / 61 page

FDC2212, FDC2214, FDC2112, FDC2114

www.ti.com

SNOSCZ5A – JUNE 2015 – REVISED JUNE 2015

Table 39. Address 0x1B, MUX_CONFIG Field Descriptions (continued)

Bit

Field

Type

Reset

Description

14:13

RR_SEQUENCE

R/W

Auto-Scan Sequence Configuration Configure multiplexing

channel sequence. The FDC will perform a single conversion on

each channel in the sequence selected, and then restart the

sequence continuously.

b00: Ch0, Ch1

b01: Ch0, Ch1, Ch2 (FDC2114, FDC2214 only)

b10: Ch0, Ch1, Ch2, Ch3 (FDC2114, FDC2214 only)

b11: Ch0, Ch1

12:3

RESERVED

R/W

00 0100

Reserved. Must be set to 00 0100 0001

0001

2:0

DEGLITCH

R/W

111

Input deglitch filter bandwidth.

Select the lowest setting that exceeds the oscillation tank

oscillation frequency.

b001: 1MHz

b100: 3.3MHz

b101: 10MHz

b111: 33MHz

9.6.30 Address 0x1C, RESET_DEV

Figure 47. Address 0x1C, RESET_DEV

RESET_DEV

RESERVED

OUTPUT_GAIN

RESERVED

Table 40. Address 0x1C, RESET_DEV Field Descriptions

Bit

Field

Type

Reset

Description

RESET_DEV

R/W

Device Reset

Write b1 to reset the device. Will always readback 0.

14:11

RESERVED

R/W

0000

Reserved. Set to b0000

10:9

OUTPUT_GAIN

R/W

Output gain control (FDC2112, FDC2114 only)

00: Gain =1 (0 bits shift)

01: Gain = 4 (2 bits shift)

10: Gain = 8 (3 bits shift)

11: Gain = 16 (4 bits shift)

8:0

RESERVED

R/W

0 0000

Reserved, Set to b0 0000 0000

0000

9.6.31 Address 0x1E, DRIVE_CURRENT_CH0

Figure 48. Address 0x1E, DRIVE_CURRENT_CH0

CH0_IDRIVE

RESERVED

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