FDC2114 datasheet(42/61 Pages) TI1

42 / 61 page

Level (mm)

4.1

4.15

4.2

4.25

4.3

4.35

4.4

4.45

4.5

4.55

4.6

4.65

4.7

D031

FDC2212, FDC2214, FDC2112, FDC2114

SNOSCZ5A – JUNE 2015 – REVISED JUNE 2015

www.ti.com

Typical Application (continued)

Figure 57. Electrodes' Capacitance vs. Liquid Level

10.2.3.2 Recommended Initial Register Configuration Values

The application requires 100SPS ( TSAMPLE = 10 ms). A sensor with an 18µH inductor and a 33pF capacitor

is used. Additional pin, trace, and wire capacitance accounts for 20pF, so the total capacitance is 53pF.

Using L and C, fSENSOR = 1/2π√(LC) = 1/2π√(18*10

-6 * 50*10-12) = 5.15 MHz. This represents the maximum

sensor frequency. When the sensor capacitance is added, the frequency will decrease.

Using a system master clock of 40 MHz applied to the CLKIN pin allows flexibility for setting the internal

clock frequencies. The sensor coils are connected to channel 0 (IN0A and IN0B pins), channel 1 (IN1A and

IN1B pins), and channel 2 (IN2A and IN2B pins).

After powering on the FDC, it will be in Sleep Mode. Program the registers as follows (example sets registers

for channel 0 only; channel 1 and channel 2 registers can use equivalent configuration):

1. Set the dividers for channel 0.

(a) Because the sensor is in an single-ended configuration, the sensor frequency select register should be

set to 2, which means setting field CH0_FIN_SELto b10.

(b) The design constraint for fREF0 is > 4 × fSENSOR. To satisfy this constraint, fREF0 must be greater than 20.6

MHz, so the reference divider should be set to 1. This is done by setting the CH0_FREF_DIVIDER field

to 0x01.

2. Sensor drive current: to ensure that the oscillation amplitude is between 1.2V and 1.8V, measure the

oscillation amplitude on an oscilloscope and adjust the IDRIVE value, or use the integrated FDC GUI feature

to determine the optimal setting. In this case the IDRIVE value should be set to 15 (decimal), which results in

an oscillation amplitude of 1.68 V(pk). The INIT_DRIVE current field should be set to 0x00. The combined

value for the DRIVE_CURRENT_CH0 register (addr 0x1E) is 0x7C00.

3. Program the settling time for Channel 0 (see Multi-Channel and Single-Channel Operation).

(a) CHx_SETTLECOUNT > Vpk × fREFx × C × π

2 / (32 × IDRIVE

X) → 7.5, rounded up to 8. To provide margin

to account for system tolerances, a higher value of 10 is chosen.

(b) Register 0x10 should be programmed to a minimum of 10.

(d) The value for Chan. 0 SETTLECOUNT register (0x10) is 0x000A.

4. The channel switching delay is ~1

μs for fREF = 40 MHz (see Multi-Channel and Single-Channel Operation)

5. Set the conversion time by the programming the reference count for Channel 0. The budget for the

conversion time is : 1/N * (TSAMPLE – settling time – channel switching delay) = 1/3 (10,000 – 4 – 1) = 3.33

(a) To determine the conversion time register value, use the following equation and solve for

CH0_RCOUNT: Conversion Time (tC0)= (CH0_RCOUNTˣ16)/fREF0.

(b) This results in CH0_RCOUNT having a value of 8329 decimal (rounded down). Note that this yields an

ENOB > 13 bits.

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