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WM8602SEDS/V Arkusz danych(PDF) 8 Page - Wolfson Microelectronics plc |
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WM8602SEDS/V Arkusz danych(HTML) 8 Page - Wolfson Microelectronics plc |
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8 / 46 page ![]() WM8602 Product Preview w PP Rev 1.5 May 2004 8 SIGNAL TIMING REQUIREMENTS POWER SUPPLY Test Conditions AGND, DGND, BGDN = 0V, TA = +25 °C PARAMETER SYMBOL MIN TYP MAX UNIT Power Supply Timing Information AVDD: rise time 10% to 90% AVDD tAR 0.2 50 ms DVDD: rise time 10% to 90% DVDD tDR 0.2 50 ms BVDD: rise time 10% to 90% BVDD tBR 0.2 50 ms Table 2 Power Supply Timing Requirements MASTER CLOCK TIMING XTI/MCLK t MCLKY Figure 1 Master Clock Timing Requirements Test Conditions AVDD, DVDD, BVDD = 3.3V, AGND, DGND, BGDN = 0V, TA = +25 °C PARAMETER SYMBOL MIN TYP MAX UNIT System Clock Timing Information XTI/MCLK System clock cycle time tMCLKY 20 100 ns XTI/MCLK Duty cycle 40:60 60:40 % XTI/MCLK Period Jitter 200 ps XTI/MCLK Rise/Fall times 10% to 90% AVDD 3 ns Table 3 Master Clock Timing Requirements |
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