WM8602SEDSSLASHV datasheet(23/46 Pages) WOLFSON

23 / 46 page

Product Preview

WM8602

PP Rev 1.5 May 2004

FOFFLRCLK

[ppm]

max

min

GAIN TIME-OUT

[ms]

±100

±1000

±10’000

~20

Table 18 Synchroniser Setup and Locking

Note: The Synchroniser requires a continuously running LRCLK. If that is not the case the HOLD

signal has to be applied to avoid the synchronizer drifting.

CONTROL INTERFACE OPERATION

SELECTION OF CONTROL MODE

The WM8602 is controlled by writing to registers through a serial control interface. A control word

consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register is

accessed. The remaining 9 bits (B8 to B0) are register bits, corresponding to the 9 bits in each

control register. The control interface can operate as either a 3-wire or 2-wire MPU interface. The

MODE pin selects the interface format. An internal pull-down resistor configures the Control Interface

to a default 2 wire format.

MODE

INTERFACE FORMAT

Low

2 wire (default)

High

3 wire

Table 19 Control Interface Mode Selection

The WM8606 Control Interface operates as a slave device only.

3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE

The WM8602 is controlled using a 3-wire serial interface. SDIN is used for the program data, SCLK

is used to clock in the program data and CSB is use to latch in the program data. The 3-wire

interface protocol is shown in Figure 13.

CSB

SCLK

SDIN

B15

B10

B11

B12

B13

B14

Figure 18 3-wire Serial Interface

The bits B[15:9] are Control Address Bits and the bits B[8:0] are Control Data Bits

2-WIRE SERIAL CONTROL MODE

The WM8602 supports software control via a 2-wire serial bus. Many devices can be controlled by

the same bus, and each device has a unique 7-bit address (this is not the same as the 7-bit address

of each register in the WM8602).

The controller indicates the start of data transfer with a high to low transition on SDIN while SCLK

remains high. This indicates that a device address and data will follow. All devices on the 2-wire bus

respond to the start condition and shift in the next eight bits on SDIN (7-bit address + Read/Write bit,

MSB first). If the device address received matches the address of the WM8602 and the R/W bit is ‘0’,

indicating a write, then the WM8602 responds by pulling SDIN low on the next clock pulse (ACK). If

the address is not recognised or the R/W bit is ‘1’, the WM8602 returns to the idle condition and wait

for a new start condition and valid address.

WM8602SEDS/V Arkusz danych(PDF) 23 Page - Wolfson Microelectronics plc

WM8602SEDS/V Arkusz danych(HTML) 23 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Arkusz danych Pobierz

Link URL