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WM8602SEDS/V Arkusz danych(PDF) 17 Page - Wolfson Microelectronics plc |
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WM8602SEDS/V Arkusz danych(HTML) 17 Page - Wolfson Microelectronics plc |
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17 / 46 page ![]() Product Preview WM8602 w PP Rev 1.5 May 2004 17 I 2S MODE In I 2S mode, the MSB is sampled on the second rising edge of BCLK following a LRCLK transition. LRCLK is low during the left samples and high during the right samples. Figure 11 I 2S Mode Timing Diagram DSP MODE A AND B In DSP mode, the Left channel MSB is available on either the 1 st (mode B) or 2nd (mode A) rising edge of BCLK (selectable by LRP) following a rising edge of LRCLK. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample. Figure 12 DSP Mode A Timing Diagram Figure 13 DSP Mode B Timing Diagram |
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