WM8602SEDSSLASHV datasheet(15/46 Pages) WOLFSON

15 / 46 page

Product Preview

WM8602

PP Rev 1.5 May 2004

Parameter

Group Delay

Unit

fs=48kHz

Unit

L / R channel

samples

1.0

SUB channel

samples

0.5

Table 9 Signal Path Group Delay

Note: The shorter delay on the SUB channel will not significantly affect audio performance. (It is

equivalent to moving the subwoofer forwards by about 15cm.)

DIGITAL AUDIO INTERFACE

The digital audio interface is used for inputting audio data into the WM8602. It uses five pins:

•

DIN: L+R channel data input

•

LRCLK: Data alignment clock

•

BCLK: Bit clock, for synchronisation

The clock signals BCLK and LRCLK can be outputs when the WM8602 operates as a master, or

inputs when it is a slave (see Master and Salve Mode Operation, below).

MASTER AND SLAVE MODE OPERATION

The WM8602 can be configured as either a master or slave mode device. As a master device the

WM8602 generates BCLK and LRCLK and thus controls sequencing of the data transfer on the data

channels. In slave mode, the WM8602 receives data and clock signals over the digital audio

interface. The mode can be selected by writing to the MS bit (see Table 23). Master and slave modes

are illustrated below.

Master Mode

Slave Mode

Figure 8 Operation Mode

AUDIO DATA FORMATS

In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK Audio

data is applied to the internal filters via the Digital Audio Interface. 5 popular interface formats are

supported:

•

Left Justified mode

•

Right Justified mode

•

2S mode

•

DSP mode A

•

DSP mode B

All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits. Except that 32

bit data is not supported in right justified mode. DIN and LRCLK are sampled on the rising, or falling

edge of BCLK.

In left justified, right justified and I

2S modes the digital audio interface receives data on the DIN input.

Audio Data for each stereo channel is time multiplexed with LRCLK indicating whether the left or right

channel is present. LRCLK is also used as a timing reference to indicate the beginning or end of the

data words.

In left justified, right justified and I

2S modes, the minimum number of BCLKs per DACLRC period is 2

times the selected word length. LRCLK must be high for a minimum of word length BCLKs and low

for a minimum of word length BCLKs. Any mark to space ratio on LRCLK is acceptable provided the

above requirements are met.

WM8602SEDS/V Arkusz danych(PDF) 15 Page - Wolfson Microelectronics plc

WM8602SEDS/V Arkusz danych(HTML) 15 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Arkusz danych Pobierz

Link URL