AD6676EBZ datasheet(37/90 Pages) AD

37 / 90 page

Data Sheet

AD6676

Rev. D | Page 37 of 90

Phase Noise Performance

Above the PLL filter bandwidth of 200 kHz, the internal VCO

limits the overall phase noise of the clock synthesizer. The VCO

phase noise performance shows a slight improvement at its low

end of its FADC operating range, as shown in Figure 100 The phase

noise for a particular IF input frequency can be calculated using

Equation 5.

PNfIN_OFFSET = PNfCLK_OFFSET + 20 × log (FIF/FADC)

(7)

For example, the phase noise at 1 MHz offset for an FADC of

3.2 GHz is approximately −124 dBc/Hz. An IF input frequency

of 200 MHz results in a 24 dB improvement, thus the expected

phase noise at 1 MHz offset is −148 dBc/Hz.

–105

–107

–109

–111

–113

–115

–117

–119

–121

–123

–125

–127

–129

–131

–133

–135

0.2

0.4

0.6

0.8

FREQUENCY OFFSET (MHz)

2.95GHz

3.00GHz

3.10GHz

3.20GHz

Figure 100. Clock Synthesizers Typical Phase Noise for Various FADC Values

The repeatability of a device that is power cycled 10 times is shown

in Figure 101. Note that the measured data in this figure aligns with

the expected results based on Equation 5 and Figure 100. The

phase noise variation over temperature of a nominal device is

shown in Figure 102.

–128

–130

–132

–134

–136

–138

–140

–142

–144

–146

–148

–150

–152

–154

–156

0.2

0.4

0.6

0.8

ZERO IF FREQUENCY OFFSET (MHz)

MEAN

–125.81

–140.93

–144.14

–146.48

STD

0.23

0.11

0.10

PK-PK

0.71

0.32

0.37

0.39

100kHz

600kHz

800kHz

1MHz

Figure 101. Power Cycle Repeatability (10 Attempts) of Phase Noise

Measurement for an IF Input Frequency of 225 MHz and fCLK = 2.94912 GHz

with PLL PFD = 61.44 MHz

–120

–124

–128

–132

–122

–126

–130

–134

–136

–138

–140

–142

–144

–146

–148

–150

–152

–154

–156

0.2

0.4

0.6

0.8

ZERO IF FREQUENCY OFFSET (MHz)

–40°C

+25°C

+85°C

Figure 102. Typical Temperature Stability of Clock Synthesizer with the Same

Conditions as Figure 101

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