AD6676EBZ datasheet(39/90 Pages) AD

39 / 90 page

Data Sheet

AD6676

Rev. D | Page 39 of 90

DIGITAL SIGNAL PROCESSING PATH

The Σ-Δ ADC provides a highly oversampled 5-bit digital

output representing the desired IF signal pass band as well as the

out-of-band shaped noise described earlier. Referring to Figure 104,

the digital signal processing path translates this oversampled

real IF signal to a complex dc centered IF signal, having a more

manageable data rate suitable for transfer via the JESD204B

interface. The QDDC performs the real-to-complex frequency

translation followed by digital filtering to remove the ADC

out-of-band noise, as well as any other undesired signal content,

before decimation to a lower data rate without any loss of

dynamic range.

–FADC/2

FADC/2

COMPLEX OUTPUT AFTER QDDC

–

fIF

–FADC/2

FADC/2

ADC REAL OUTPUT

DESIRED

SIGNAL

ADC NOISE

IMAGE

SIGNAL

COMPLEX OUTPUT AFTER DECIMATION

–

fDATA_IQ/2

COMPLEX OUTPUT AFTER FILTERING

–FADC/2

FADC/2

DIGITAL FILTER RESPONSE

Figure 104. Digital Signal Processing Path Performs Frequency Translation to

a Zero IF as well as Filtering and Downsampling

Quadrature Digital Downconversion

Digital downconversion occurs in two stages using a coarse and

a fine QDDC. As shown in Figure 103, the coarse QDDC

resides immediately after the Σ-Δ ADC and the fine QDDC

follows the first decimation stage. The coarse QDDC provides

6-bit tuning resolution whereas the fine QDDC provides 10-bit

tuning resolution. The composite tuning resolution is either

FADC/3072 or FADC/4096, depending on whether the first

decimation stage is configured for 3× or 4× decimation, which

in turn depends on the decimation mode selected as described

in Table 13. For applications requiring finer tuning resolution to

position the IF signal exactly about dc, consider adding a finer

resolution QDDC in the host processor.

Table 13. Finite Composite Tuning Resolution of Coarse and

Fine NCO

DEC_MODE

(Register 0x140,

Bits[2:0])

Decimation

Factor

Tuning

Resolution

Tuning Res.

(MHz) at FADC =

3.072 GSPS

FADC/4096

0.75

FADC/3072

1.00

FADC/4096

0.75

FADC/3072

1.00

The tuning frequency settings of the combined coarse and

fine NCO (SPI Register 0x141 and SPI Register 0x142) are

automatically calculated and set by the AD6676 during the

device SPI initialization phase. The user defined FADC and IF

settings (SPI Register 0x100 thru SPI Register 0x103) are used

to calculate the settings such that the center of the IF pass band

is centered about dc. The coarse tuning NCO is set via

MIX1_TUNING[5:0], whereas the fine tuning NCO is set via

MIX2_TUNING[7:0]. The decimal equivalent frequency setting

of each NCO register is based on the following equations.

















ADC

MIX1

Round

(8)

where:

MIX1 is a 6-bit binary number representing the NCO frequency

setting in MIX1_TUNING.

FIF is the desired carrier frequency in hertz (Hz).

FADC is the ADC clock rate in hertz (Hz).































Round

MIX1

MIX2

ADC

(9)

where:

MIX2 is a 8-bit twos complement number representing the

NCO frequency setting in MIX2_TUNING.

M is 3072 for DEC_MODE = 2 and 4, or 4096 for DEC_MODE =

1 and 3.

It is important to note the residue, fOFFSET, between the desired

FIF and the AD6676 composite NCO setting, FIF_NCO, because

any offset may need to be compensated with an additional fine

QDDC located in the host processor. Use the following

equations to calculate both parameters:

ADC

NCO

MIX2

MIX1



















(10)

fOFFSET = FIF – FIF_NCO

(11)

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