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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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AD6676EBZ Arkusz danych(PDF) 10 Page - Analog Devices |
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AD6676EBZ Arkusz danych(HTML) 10 Page - Analog Devices |
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10 / 90 page  AD6676 Data Sheet Rev. D | Page 10 of 90 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDDQ VDD1 VSSA VDD1 VDD2 L+ L– VSSA 12345 678 CLK+ VDD1 VDD1 VSSA VDD1 VDD2 VDD2 VIN+ CLK– VDDC VDD1 VDD1 VSSA VDD1 VSSA VIN– VDDC VDDC VDD1 VDDL VDDL VSSA VDD1 VSSA VSSA VSSA VSSA VSSA VSSA VSSA VDD2 VDD2 VSSA VSSA VSSA VSSD VSSD VSS2IN VDD2NV VSSA SYSREF+ VSSD VSSD VSSD VSSD RESETB VSS2OUT VDDIO SYSREF– VSSD VDDD VDDD VDDD SDO AGC4 AGC2 VDDHSI VDDHSI VDDD VDDD VDDD CSB AGC3 AGC1 SERDOUT0– 1.1V ANALOG SUPPLY SERDOUT0+ SERDOUT1– SERDOUT1+ SYNCINB+ SYNCINB– SCLK SDIO A B C D E F G H J K 1.1V DIGITAL SUPPLY ANALOG SUPPLY GROUND 2.5V ANALOG SUPPLY –2V ANALOG SUPPLY DIGITAL SUPPLY GROUND SPI INTERFACE ADC I/O 1.8V TO 2.5V DIGITAL I/O ANALOG SUPPLY AGC I/O JESD204B INTERFACE Figure 3. Pin Configuration (Top View, Not to Scale) Table 6. Pin Function Descriptions Pin No. Mnemonic Description Σ-Δ ADC Modulator B8, C8 VIN+, VIN− Analog Inputs with Nominal 60 Ω Differential Input Termination. A6, A7 L+, L− Analog Outputs for External Inductor. B1, C1 CLK+, CLK− Clock Inputs, Nominal 100 Ω Differential Input Termination When the Clock Synthesizer is Disabled. When the clock synthesizer is enabled, each input is 1.2 kΩ; therefore, an external, 100 Ω differential termination is recommended if the clock source is LVDS or PECL. For a CMOS source driving a long trace, the addition of a series 33 Ω resistor next to the source reduces overshoot seen at CLK+ input pin. JESD204B Interface K1, K2 SERDOUT0−, SERDOUT0+ Lane 0 JESD204B Digital CML Outputs. K3, K4 SERDOUT1−, SERDOUT1+ Lane 1 JESD204B Digital CML Outputs. G1, H1 SYSREF+, SYSREF− JESD204B SYSREF Inputs. Note that these pins have no differential termination. K5, K6 SYNCINB+, SYNCINB− JESD204B CMOS or LVDS SYNC Inputs. Selectable via Register 0x1E7, Bit 2. Default CMOS mode uses the SYNCINB+ pin only. LVDS mode has a 100 Ω differential termination. |
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