AD6676EBZ datasheet(6/90 Pages) AD

6 / 90 page

AD6676

Data Sheet

Rev. D | Page 6 of 90

Parameter

Temperature

Test Conditions/Comments

Min

Typ

Max

Unit

CLOCK SYNTHESIZER

Phase Detector Frequency

Full

MHz

Minimum Charge Pump Output Current

Full

0.1

Maximum Charge Pump Output Current

Full

6.4

VCO Tuning Range

Full

2.94

3.2

GHz

Σ-∆ ADC AND DIGITAL DOWNCONVERTER

Resolution

Full

Bits

Clock Frequency (FADC)

Full

2.0

3.2

GHz

IF Center Frequency (FIF)

Full

450

MHz

IF Bandwidth

Maximum BW applies to

higher FIF

0.005

× FADC

0.05 ×

FADC

IF Pass Band Gain Flatness

Full

FADC, FIF, and BW dependent

1.0

Out-of-Band Peaking

Depends on FADC, FIF, and BW

0.5

Alias Rejection

Regions of FADC ± FIF

Fixed Decimation Factors

Full

12, 16, 24,

NCO Tuning Resolution

Decimate by 12 or 24

FADC/3072

Decimate by 16 or 32

FADC/4096

Out-of-Range Recovery Time

Full

Relative to ADC clock cycles

1/FADC

POWER SUPPLY AND CONSUMPTION

Analog Supply Voltage

VDD1, VDDL, VDDQ, VDDC

Full

1.0725

1.1

1.1275

VDD2, VDD2NV

Full

2.4375

2.5

2.5625

VSS2IN

Use on-chip regulator, tie to

VSS2OUT

−2.0

Digital Supply Voltage (VDDD)

Full

1.0725

1.1

1.1275

JESD204B Supply Voltage (VDDHSI)

Full

1.0725

1.1

1.1275

SPI Interface Supply Voltage (VDDIO)

Full

1.7

1.8

2.5625

Analog Supply Current

IVDD1 + IVDDL

Full

368

397

IVDDC + IVDDQ

Full

CLK synthesizer disabled

IVDDC4 + IVDDQ

Full

CLK synthesizer enabled

106

IVDD2 + IVDD2NV

Full

145

165

Digital Supply Current (IVDDD)

Full

141

208

JESD204B Supply Current (IVDDHSI)

Full

164

190

SPI Interface Supply Current (IVDDIO)

Full

0.4

Power Consumption

Full

With CLK SYN Disabled

1.16

1.31

With CLK SYN Enabled

1.20

1.34

Standby5

Full

0.44

Power-Down

Full

177

OPERATING TEMPERATURE RANGE

−40

+85

°C

1 Extrapolated input power level is measured at the center of IF pass band that results in a 0 dBFS power level.

2 The overload level of the Σ-Δ

ADC for a CW tone is guaranteed up to −2 dBFS back oﬀ from full scale but typically exceeds −1 dBFS. Input signals that have a higher

peak-to-average ratio (PAR) than a CW tone (PAR = 3 dB) must apply additional back off based on the difference in PAR.

3 The clock synthesizer reference divider (Register 0x2BB, Bits[7:6]) must be set to divide by 4 or by 2 to ensure that its phase detector frequency remains ≤40 MHz.

4 fCLK = 200 MHz, FADC = 3.2 GHz.

5 The AD6676 is configured for recovery time of 11.5 μs with VSS2 generator/ digital data in standby (Register 0x150 = 0x40) and low power ADC state (Register 0x250 = 0x95).

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