AD6676EBZ datasheet(61/90 Pages) AD

61 / 90 page

Data Sheet

AD6676

Rev. D | Page 61 of 90

AD6676 START-UP INITIALIZATION

On power-up of the AD6676, a host processor is required to

initialize and configure the AD6676 via its SPI port. Figure 145

shows a flowchart of the sequential steps required to bring the

AD6676 to an operational state. The number of SPI writes and total

initialization time is dependent on whether the clock synthesizer

is used, as well as any additional configuration associated with the

AGC features or its pin configurations. Note that wait states are

required during different steps in the initialization process to

allow various actions, such as calibration and tuning, to be

completed before moving to the next step.

Table 26 shows the minimum SPI writes required to enable the

AD6676. Note the following in the sequence of steps shown in

Table 26:



The example SPI writes pertain to the following settings:

FADC = 3.200 GHz, FO = 250 MHz, BW = 100 MHz, IDAC1FS =

2 mA, MRGN_L = MRGN_U = 10 MHz, MRGN_IF =

1 MHz, fDATA_IQ = 200 MSPS with decimate by 16, and fREF =

200 MHz with the clock synthesizer enabled.



Step 3 refers to Table 28 for the necessary SPI writes when

the clock synthesizer is enabled or disabled, respectively.

Example AGC parameters are included in Table 29 but are

nonessential to device operation.



The RESON1 calibration for the ADC occurs first with default

DEC_MODE setting. DEC_MODE is updated to the user

specified setting prior to JESD204B calibration.



ADC and JESD204B calibration and initialization must be

successful on first attempt. However, Step 24 and Step 30 are

included to provide coverage against external events (supply

or clock glitch) that can corrupt this process.

The AD6676EVB software GUI has an option that automatically

generates and saves the series of SPI writes in the .csv file

format, as shown in Table 25, which is the preferred method for

generating the AD6676 SPI write initialization sequence. Note

the following:



The SPI sequence can be shorter when the AD6676EVB

development platform is connected to the PC because the

software also performs a SPI read back and then only

writes to those SPI registers that have been changed from

its default setting.



To generate a SPI initialization sequence for an alternative

development platform, ensure that the AD6676EVB

development platform is disconnected from the PC



When the software GUI is configured for the profile feature,

and ADC profile, respectively, that pertain to the specific

ADC application parameter settings in Register 0x100 thru

process repeats itself for the remaining specified profiles.

HARDWARE OR

SOFTWARE

RESET

AD6676

OPERATIONAL

PROGRAM CONFIGURATION SETTINGS

JESD204B CONFIGURATION

ADC PARAMETERS

RUN ADC CAL + JESD204B

INITIALIZATION

CALIBRATION + TUNING

INITIALIZE

CLK SYN

INITIALIZE

RF CLK

PATH

WAIT

(2ms)

WAIT

(400ms)

CLK SYN?

YES

CAL OK?

YES

ADC CAL/TUNE ERROR

(MAKE TWO MORE

ATTEMPTS)

ALL REGISTERS

RETURNED

TO DEFAULT

PROGRAM OPTIONAL SETTINGS

AGC CONFIGURATION

ADC SHUFFLER

RUN RESON1 CAL

WITH DEC_MODE=1

WAIT

(400ms)

CAL OK?

YES

RESON1 TUNE ERROR

(MAKE TWO MORE

ATTEMPTS)

PROGRAM DECIMATION MODE

Figure 145. Flowchart for Initialization and Configuration of the AD6676

Table 25. Example of Saved .CSV File Format

Write

0x000

0x99

0x2A5

0x05

0x2A0

0xC0

…

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