STV3550 datasheet(58/144 Pages) STMICROELECTRONICS

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STV3550

Output Stage

Obviously, the value of the DELAY_RISE and DELAY_FALL values must be compatible with the

GFX_ACTIVE signal waveform. For example, if DELAY_RISE = 0111 and DELAY_FALL = 0000,

the ninimum duration of the high level of the GFX_ACTIVE signal must be 10 CLK_DAC clock

cycles.

0011

CSA Stage Number - 4 clock cycles

0011

CSA Stage Number - 4 clock cycles

0100

CSA Stage Number - 3 clock cycles

0100

CSA Stage Number - 3 clock cycles

0101

CSA Stage Number - 2 clock cycles

0101

CSA Stage Number - 2 clock cycles

0110

CSA Stage Number - 1 clock cycle

0110

CSA Stage Number - 1 clock cycle

0111 (Standard)

CSA Stage Number

0111 (Standard)

CSA Stage Number

1000

CSA Stage Number + 1 clock cycle

1000

CSA Stage Number + 1 clock cycle

1001

CSA Stage Number + 2 clock cycles

1001

CSA Stage Number + 2 clock cycles

1010

CSA Stage Number + 3 clock cycles

1010

CSA Stage Number + 3 clock cycles

1011

CSA Stage Number + 4 clock cycles

1011

CSA Stage Number + 4 clock cycles

1100

CSA Stage Number + 5 clock cycles

1100

CSA Stage Number + 5 clock cycles

1101

CSA Stage Number + 6 clock cycles

1101

CSA Stage Number + 6 clock cycles

1110

CSA Stage Number + 7 clock cycles

1110

CSA Stage Number + 7 clock cycles

1111

CSA Stage Number + 8 clock cycles

1111

CSA Stage Number + 8 clock cycles

Table 15: Delay on Rising/Falling Edges of GFX_ACTIVE Signal

DELAY_RISE

Delay Value

DELAY_FALL

Delay Value

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