STV3550 datasheet(88/144 Pages) STMICROELECTRONICS

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STV3550

7.2

Infrared Receiver Preprocessor

The Infrared Receiver (IR) Preprocessor measures the interval between adjacent edges of the

demodulated output signal from the IR amplifier/detector. Control bits determine whether the

intervals of interest involve consecutive positive edges, negative edges, or any two edges. The

measurement is represented in terms of 64.133 kHz clock cycles.

Whenever an edge of specified polarity is detected, the number of clock cycles counted since the

previously detected edge is latched into the first of two 12-bit registers (IRP0 and IRP1) and an

interrupt request is generated. When the interrupt is detected, the value of register IRP0 is read and

this value used to calculate the interval between the two specified consecutive edges.

At the counter overflow, the counter value is latched immediately and an interrupt is generated.

If a new edge of the specified polarity is detected or if the counter overflows and register IRP0 does

not contain its maximum value before it is read, the value of register IRP0 is latched into register

IRP1 if this register is empty. If register IRP1 is not empty, the new value is stored in register IRP0.

If a new edge is detected and if both registers (IRP0 and IRP1) are not empty, the new edge cannot

be taken into account until both registers are reset. (The interval is not measured.)

An internal algorithm is used to reset the flags and register values.

The IR input signal is preprocessed by a spike filter that determines whether all pulses narrower

than either 2 µs or 160 µs are filtered out before the signal is applied to the edge detector.

Figure 56: Infrared Receiver Diagram

12-bit Counter

Error Flag

Control

64.133 kHz Clock

Interrupt

IR Input

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