STV3550 datasheet(100/144 Pages) STMICROELECTRONICS

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STV3550

The phase bit, SSCPH, indicates whether a pulse is generated in the first or second half of the

cycle. Note that this is a pulse relative to the idle state of the clock line i.e. if polarity is 0 then the

pulse is positive going, if polarity is 1 then the pulse will be negative going. A phase setting of 0

causes the pulse to be in the second half of the cycle, a setting of 1 causes the pulse to occur in the

first half of the cycle. The different combinations of polarity and phase are shown in Figure 64.

The SSC2 will always latch incoming data in the middle of the clock period at the point shown in the

diagram. With the different combinations of polarity and phase it is possible to generate or not

generate a clock pulse before the first data bit is latched.

Shifting out of data occurs at the end of the clock period. At the start of the first clock period the shift

buffer.

Baud Rate Generation

The SSC2 can generate a range of different baud rate clocks in master mode. These are setup by

programming the baud rate generator register, SSCBRG.

Writing this register programs the baud rate as defined by the following formulas.

Where SSCBRG represents the content of the reload register, as an unsigned 16 bit integer and

fCPU represents the CPU clock frequency.

Figure 64: Clock Polarity And Phase Control

SSCPO SSCPH

SDA Pin

Latch Shift Latch ShiftLatch Unload

Latch Shift Latch Shift Latch Unload

Load

Baudrate

CPU

2xSSCBRG

----------------------------------

=SSCBRG

CPU

2xBaudrate

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