STV3550 datasheet(71/144 Pages) STMICROELECTRONICS

71 / 144 page

CPU and System Management Functional Description

STV3550

71/144

6.3.8.3 Default Settings For Boot Operation

The STV3550 system clock frequency is 27 MHz when the boot sequence is executed. Below are

the default settings of the STV3550 Memory Interface:

●

Access Cycle Time (tAC) is 20 cycles (740 ns)

●

Bus Release Time (tBR) is 4 cycles

●

Data Drive Delay (tDD) is 10 phases

●

Falling edge of NOT_CS_FLASH after start of Read Access Cycle (tCSr1) is 0

●

Rising edge of NOT_CS_FLASH after start of Read Access Cycle (tCSr2) is 0

●

Falling edge of NOT_CAS (NOT_OE) after start of Read Access Cycle (tOE1) is 0

●

Rising edge of NOT_CAS (NOT_OE) after start of Read Access Cycle (tOE2) is 0

●

Latch Point (tLP) before end of Access Cycle is 0

●

NOT_CS_FLASH is active during read only

●

NOT_CAS (NOT_OE) is active during read only

●

RD_NOT_WR is never active (only read operations authorized)

6.3.9

STV3550 Memory Interface Capabilities Regarding SDRAM Device

6.3.9.1 Supported SDRAM Commands

The STV3550 Memory Interface supports the following SDRAM commands:

●

Mode Register Set

●

Row Activate

●

Precharge All

Figure 43: Access Cycle Timings

tLP

tBR

tDD

tCSr1/tCSw1

tCSr2/tCSw2

tOE1

tAC

ADDR[19:0]

NOT_CS_FLASH

NOT_CAS

FLASH_D[15:0]

(write)

FLASH_D[15:0]

(read)

tOE2

(NOT_OE)

tWE1

RD_NOT_WR

tWE2

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