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Zakładka z wyszukiwarką danych komponentów |
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STV3550 Arkusz danych(PDF) 75 Page - STMicroelectronics |
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STV3550 Arkusz danych(HTML) 75 Page - STMicroelectronics |
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75 / 144 page  CPU and System Management Functional Description STV3550 75/144 6.3.10 SDRAM Low Power Mode The STV3550 is able to set the SDRAM into Low Power mode. Most SDRAM devices have a Clock Enable input pin that internally gates the SDRAM clock supplied by the STV3550. The STV3550 does not have the corresponding output pin included in its memory interface, but this feature can be emulated using any of the standard STV3550 I/Os. Figure 46: Typical Read Access Cycle (CAS Latency = 2) Figure 47: Typical Refresh Access Cycle NOT_RAS NOT_CAS RD_NOT_WR NOT_BE[1:0] SDRAM_D[15:0] RAS to CAS PrechargeTime ADDR[16:15], Row Column Row Read activate CKOUT_SDRAM NOT_CS_SDRAM N Column M CAS Latency =2 Precharge All AP=1 NOP NOP BusReleaseTime ADDR[11:0] (ADDR[19:18]) (FLASH_D[15:0]) DQM high to data out forced to High-Z equals to 2 clock cycles (fixed NOT_BE latency for reads). NOT_RAS RD_NOT_WR RefreshTime NOT_CS_SDRAM CKOUT_SDRAM PrechargeTime NOT_CAS 1 cycle |
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