STLC5465B datasheet(70/101 Pages) STMICROELECTRONICS

70 / 101 page

MBL

: Memory Bus Low impedance

MBL = 1, the shared memory bus is at low impedance between two memory cycles.

The memory bus includes Control bits, Data bits, Address bits. One

Multi-HDLC is connected to

the shared memory.

MBL = 0, the shared memory bus is at high impedance between two memory cycles.

Several Muti-HDLCs can be connected to the shared memory. One pull up resistor is

recommended on each wire.

SBV

: Six Bit Validation (A, E, S1/S4 bits). Global validation for 16 channels (Upstream and

downstream).

SBV = 1, in reception, the six bit word (A, E, S1/S4) located in the same timeslot as D channel

can be received from any input timeslot; when this word is received identical twice consecutively,

it is stored in the external shared memory and an interrupt is generated if not masked (like the

reception of primitive from C/I channel). See “RECEIVE Command/Indicate INTERRUPT” on

page 97.

Sixteen independent detections are performed if the contents of any input timeslot is switched

in the timeslot 4n+3 of two GCI multiplexes (corresponding to DOUT4 and DOUT5) with (0 £ n

£ 7). Only the contents of D channel will be transmitted from input timeslot to GCI multiplexes.

From ISDN channels to GCI channels on page 34.

In transmission a six bit word (A, E, S1/S4) can be transmitted continuouslyto any output timeslot

via the TCIR. See “Transmit Command/Indicate Register TCIR (2A)H” on page 76. This word

(A, E, S1/S4) is set instead of primitive (C1, C2, C3, C4) and A, E bits received from the timeslot

4n+3 of two GCI multiplexes and the new contents of this timeslot 4n+3 must be switched on

the selected output timeslot.

SBV=0, the 16 six bit detections are not validated.

VIII.3 - Input Multiplex Configuration Register 0 - IMCR0 (04)H

bit15

bit8

bit7

bit 0

LP3 DEL3 ST(3)1 ST(3)0

LP2 DEL2 ST(2)1 ST(2)0 LP1 DEL1 ST(1)1 ST(1)0 LP0 DEL0 ST(0)1 ST(0)0

After reset (0000)H

See definition in next Paragraph.

VIII.4 - Input Multiplex Configuration Register 1 - IMCR1 (06)H

bit15

bit8

bit7

bit 0

LP7 DEL7 ST(7)1 ST(7)0

LP6 DEL6 ST(6)1 ST(6)0 LP5 DEL5 ST(5)1 ST(5)0 LP4 DEL4 ST(4)1 ST(4)0

After reset (0000)H

ST(i)0 : STEP0 for each Input Multiplex i(0

≤ i ≤ 7), delayed or not.

ST(i)1 : STEP1 for each Input Multiplex i(0

≤ i ≤ 7), delayed or not.

DEL(i); : DELAYED Multiplex i(0

≤ i ≤ 7).

DEL (i) ST (i) 1 ST (i) 0

STEP for each Input Multiplex 0/7 delayed or not

Each received bit is sampled at 3/4 bit-time without delay.

First bit of the frame is defined by Frame synchronization Signal.

Each received bit is sampled with 1/2 bit-time delay.

Each received bit is sampled with 1 bit-time delay.

Each received bit is sampled with 2 bit-time delay.

Each received bit is sampled with 1/2 bit-time advance.

Each received bit is sampled with 1 bit-time advance

Each received bit is sampled with 2 bit-time advance.

When IMTD = 0 (bit of SMCR), DEL = 1 is not taken into account by the circuit.

1/2 bit time 244ns if TDM at 2048 kHz,

1/2 bit time 122ns if TDM at 4096 kHz.

VIII - INTERNAL REGISTERS (continued)

STLC5465B

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