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STLC5465B Arkusz danych(PDF) 17 Page - STMicroelectronics

Numer części STLC5465B
Szczegółowy opis  MULTI-HDLCWITH n x 64 SWITCHING MATRIX ASSOCIATED
PDF  101 Pages
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Producent  STMICROELECTRONICS [STMicroelectronics]
Strona internetowa  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STLC5465B Arkusz danych(HTML) 17 Page - STMicroelectronics

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background image
OTSy, OTDMq
DATA
MEMORY
n x 64kb/s
DATA
MEMORY
n x 64kb/s
DOWN STREAM
ITSy, ITDMq
UP STREAM
ITSx,ITDMp
DOWN STREAM
OTSx, OTDMp
UP STREAM
Bidirectional Connection
OTSy, OTDMq
DATA
MEMORY
n x 64kb/s
DOWN STREAM
ITSx,ITDMp
DOWN STREAM
Unidirectional Connection
p, q = 0 to 7
x, y = 0 to 31
Figure 3 : Unidirectional and Bidirectional Connections
OTSy, OTDMq
DATA
MEMORY
n x 64kb/s
DATA
MEMORY
n x 64kb/s
DOWN STREAM
ITSy, ITDMq
UP STREAM
ITSx,ITDMp
DOWN STREAM
OTSx, OTDMp
UP STREAM
OTSV
Loop
Loopback per channel relevant if bidirectional connection has been done.
p, q = 0 to 7
x, y = 0 to 31
Figure 4 : Loop Back
III - FUNCTIONAL DESCRIPTION (continued)
III.1.5 - Delay through the Matrix
III.1.5.1 - Variable Delay Mode
In the variable delay mode, the delay through the
matrix dependson the relative positions of the input
and output time slots in the frame.
So, some limits are fixed :
- the maximum delay is a frame + 2 time slots,
- the minimum delay is programmable.
Three time slots if IMTD = 1, in this case n = 2 in
the formula hereafter or two time slots if
IMTD = 0, in this case n = 1 in the same formula
(see Paragraph ”Switching Matrix Configuration
Reg SMCR (0C)H” on Page 64).
All the possibilities can be ranked in three cases :
a) If OTSy > ITSx + n then the variable delay is :
OTSy - ITSx Time slots
b) If ITSx < OTSy < ITSx + n then the variable delay
is :
OTSy - ITSx + 32 Time slots
c) OTSy < ITSx then the variable delay is :
32 - (ITSx - OTSy) Time slots.
N.B. Rule b) and rule c) are identical.
For n = 1 and n = 2, see Figure 5 on Page 18.
III.1.5.2 - Sequence Integrity Mode
In the sequence integrity mode (SI = 1, bit located
in the Connection Memory), the input time slots are
put out 2 frames later (fig. 6 - page 19). In this case,
the delay is defined by a single expression :
Constant Delay = (32 - ITSx) + 32 + OTSy
So, the delay in sequence integrity mode varies
from 33 to 95 time slots.
STLC5465B
17/101



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