STLC5465B datasheet(3/101 Pages) STMICROELECTRONICS

3 / 101 page

TABLE OF CONTENTS (continued)

Page

III - FUNCTIONAL DESCRIPTION (continued)

III.3.4 - CI and Monitor Channel Configuration . . . ..... ...... .. .... . . . . . . . 30

III.3.5 - CI and Monitor Transmission/Reception Command

. . . . . . . . . . . . . ..... . . 30

III.4 - Microprocessor Interface . . . . . . . .... . . ..... ..... . . ..... .. . . . 34

III.4.1 - Description

. . . . . . . .... . . ... ....... . . ..... .. . . . . . . . . . 34

III.4.2 - Exchange with the shared memory . . . . . . .... ... ..... ..... . . .... 35

III.4.2.1 - Write FIFO

. . . . . . . . . . . . .... .. . .... . . .. . . . . . . .... . . . 35

III.4.2.2 - Read Fetch Memory

. . . . . . . .... . . ..... ..... . . ..... .. . . . 35

III.4.3 - Definition of the Interface for the different microprocessors . . . . ...... ... .... 35

III.5 - Memory Interface . . . . . . . .... . . ... .... . . . . . . . . .... . . ... ..38

III.5.1 - Function Description

. . . . . . . . . . . . . . . . . . . . . . . ..... ........ 38

III.5.2 - Choice of memory versus microprocessor and capacity required

. . . . ...... ... 38

III.5.3 - Memory Cycle

. . . . . . . .... . . ... .... . . . . . . . . .... . . ... ..38

III.5.4 - SRAM interface . . . . . . . .... . . ... .... . . . . . . . . .... . . ... ..39

III.5.5 - DRAM Interface . . . . . . . .... . . ... .... . . . . . . . . .... . . ... ..39

III.5.4.2 - 512K x n SRAM . . . . . . . . . . . . ...... ..... .... . . ... ...... 39

III.5.5.2 - 1M x n DRAM Signals . . . . . . . .... . . ..... ..... . . ..... .. . . . 40

III.5.5.3 - 4M x n DRAM Signals . . . . . . . .... . . ..... ..... . . ..... .. . . . 40

III.6 - Bus Arbitration

. . . . . . . . . . . . .... .. . .... . . .. . . . . . . .... . . . 40

III.7 - Clock Selection and Time Synchronization . . . . . . . . . . . . . ..... ..... . . . 41

III.7.1 - Clock Distribution Selection and Supervision . . . . .... .. . . . . . . . . . . . . . . 41

III.7.2 - VCXO Frequency Synchronization . . . . . . .... ... ..... ..... . . .... 41

III.8 - Interrupt Controller . . . . . . . . . . . . ...... ..... .... . . ... ...... 42

III.8.1 - Description . . . . . . . .... . . ... ....... . . ..... .. . . . . . . . . . 42

III.8.2 - Operating Interrupts (INT0 Pin) . . . . . . . . . . . . . . ...... .. . . ... ... . 42

III.8.3 - Time Base Interrupts (INT1 Pin)

. . . . . . . . . . . . . . . . . . . . . . . ..... . . 42

III.8.4 - Emergency Interrupts (WDO Pin) . . . . . . . . . . . . . . . . . . . . . . . ..... . . 42

III.8.5 - Interrupt Queues . . . . . . . . . . . . ...... ..... .... . . ... ...... 42

III.9 - Watchdog . . . . . . . .... . . ... ...... . . ... ...... ..... . . . . . 43

III.10 - Reset . . . . . . . . . . .... .. . . . ... . ... .. . . . .... . . ... . . . . . 43

III.11 - Boundary Scan

. . . . . . . .... . . ... .... . . . . . . . . .... . . ... ..43

IV - DC SPECIFICATIONS . . . . . . . .... . . ... .... . . . . . . . . .... . . ... ..44

IV.1 - Absolute Maximum Ratings . . . . . . . . . . ..... .. . . .... . . .. . . . . . . . 44

IV.2 - Power Dissipation . . . . . . . .... . . ... .... . . . . . . . . .... . . ... ..44

IV.3 - Recommended DC Operating Conditions

. . . . . . . . . . . . . ..... ..... . . . 44

IV.4 - TTL Input DC Electrical Characteristics . . . . . . . . . ...... .. . . .... . . ... 44

IV.5 - CMOS Output DC Electrical Characteristics . . . . . . . . . . . . . . ...... .. . . . 44

IV.6 - Protection . . . . . . . .... . . ... ...... . . ... ...... ..... . . . . . 44

V - CLOCK TIMING ... .. . . .... . . ... ...... . . ... ...... ..... . . . . . 45

V.1 - Synchronization Signals delivered by the system . . . . ...... ... ..... ..... 45

V.2 - TDM Synchronization . . . . . . . .... . . ....... .. . . ... ...... .... 46

V.3 - GCI Interface

. . . . . . . .... . . ... ....... . . ..... .. . . . . . . . . . 47

V.4 - V* Interface . . . . . . . . . . . . .... ..... . . ..... ....... .. ... . . 48

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