STLC5465B datasheet(21/101 Pages) STMICROELECTRONICS

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III.1.6 - Connection Memory

III.1.6.1 - Description

The connection memory is composed of 256 loca-

tions addressed by the number of OTDM and TS

(8x32).

Each location permits :

- to connect each input time slot to one output time

slot (If two or more output time slots are con-

nected to the same input time slot number, there

is broadcasting).

- to select the variable delay mode or the sequence

integrity mode for any time slot.

- to loop back an output time slot. In this case the

contents of an input time slot (ITSx, ITDMp) is the

same as the output time slot (OTSx,OTDMp).

- to output the contents of the corresponding con-

nection memory instead of the data which has

been stored in data memory.

- to output the sequence of the pseudo random

sequence generator on an output time slot: a

pseudo random sequence can be inserted in one

or several time slots (hyperchannel) of the same

Output TDM ; this insertion must be enabled by

the microprocessor in the configuration register

of the matrix.

- to define the source of a sequenceby the pseudo

random sequence analyzer: a pseudo random

sequence can be extracted from one or several

time slots (hyperchannel)of the same Input TDM

and routed to the analyzer; this extraction can be

enabled by the microprocessor in the configura-

tion register of the matrix (SMCR).

- to assert a high impedance level on an output

time slot (disconnection).

- to deliver a programmable 256-bit sequence dur-

ing 125 microsecondson the Programmable syn-

chronization Signal pin (PSS).

III.1.6.2 - Access to Connection Memory

Supposing that the Switching Matrix Configuration

microprocessor, it is possible to access to the con-

nection memory from microprocessor with the help

of two registers :

- Connection Memory Data Register (CMDR) and

- Connection Memory Address Register (CMAR).

III.1.6.3 - Access to Data Memory

To extract the contents of the data memory it is

possible to read the data memory from microproc-

essor with the help of the two registers :

- Connection Memory Data Register (CMDR) and

- Connection Memory Address Register (CMAR).

III.1.6.4 - Switching at 32 Kbit/s

Four TDMs can be programmed individually to

carry 64 channels at 32 Kbit/s (only if these TDMs

are at 2 Mbit/s).

Two bits (SW0/1) located in SMCR define the type

of channels of two couples of TDMs.

SW0 defines TDM0 and TDM4 (GCI0) and SW1

defines TDM1 and TDM5 (GCI1). If TDM0 or/and

TDM1 carry 64 channels at 32 Kbit/s then TDM2

or/and TDM3 are not available externally they are

used internally to perform the function.

Downstream switching at 32 kb/s on page 22.

Upstream switching at 32 kb/s on page 23.

III.1.6.5 - Switching at 16 kbit/s

The TDM4 and TDM5 can be GCI multipexes.Each

GCI multipexcomprises 8 GCI channels.Each GCI

channel comprises one D channel at 16 Kbit/s.See

GCI channel definition GCI Synchro signal deliv-

ered by the Multi-HDLC on page 30.

It is possibleto switch the contentsof 16 D channels

from the 16 GCI channels to 4 timeslots of the 256

output timeslots.

In the other direction the contents of an selected

timeslot is automatically switched to 4 D channels

at 16 Kbit/s.

See Connection Memory Data Register CMDR

(0E)H on page 74

III - FUNCTIONAL DESCRIPTION (continued)

STLC5465B

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