STLC5465B datasheet(35/101 Pages) STMICROELECTRONICS

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III.4.2 - Exchange with the shared memory

A Fetch Buffer located in the microprocessor inter-

face allows to reduce the shared memory access

cycle for the microprocessor.

It is used whatevermicroprocessor selectedthanks

to MOD0/2 pins.

This Fetch Buffer consists of one Write FIFO and

four Read Fetch Memories.

III.4.2.1 - Write FIFO

When the microprocessor delivers the address

word named An to write data named [An] in the

shared memory in fact it writes data [An] and

addressword An in the Write FIFO (Deep 4 words).

If An is in Fetch Memory, [An] is removed in Fetch

Memory.

The number of wait cycles for the microprocessor

is strongly reduced.

III.4.2.2 - Read Fetch Memory

When the microprocessor delivers the address

word named An to read data named [An] out of the

shared memory in fact it reads data [An] from one

of four Read Fetch Memories.

The number of wait cycle for the microprocessor is

strongly reduced and can reach zero when An,

addressword delivered by the microprocessor, and

data [An] is already in the Read Fetch Memory and

validated.

The source of [An] is truly the shared memory

whatever An.

III.4.3 - Definition of the Interface for the differ-

ent microprocessors

The signals connected to the microprocessor inter-

face are presented on the following figures for the

different microprocessor.

Shared memory

To shared memory

From shared memory

Write FIFO

An, [An]

microprocessor

interface

Read Fetch

Memory

Four

Fetch Memories

An, [An]

An+1, [An+1]

An+2, [An+2]

An+3, [An+3]

From microprocessor

To microprocessor

Microprocessor

Figure 17.1: Write FIFO and Fetch Memories.

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