STLC5465B datasheet(97/101 Pages) STMICROELECTRONICS

97 / 101 page

Receiver

: Tx = 0, Receiver

A4/0

: Rx HDLC Channel 0 to 31

ERF

: Error detected on Received Frame

An error such as CRC not correct, Abort, Overflow has been detected.

EOQ

: End of Queue

The receive DMA Controller has encountered the current receive Descriptor with EOQ at ”1”.

DMA Controller is waiting ”Continue” from microprocessor.

HALT

: The Receive DMA Controller has received HALT or ABORT (on the outside of frame) from the

microprocessor; it is waiting ”Continue” from the microprocessor.

: Buffer Filled

If IBC bit of Receiver Descriptor is at ‘1’, the Receive DMA Controller puts BF at”1” when it has

filled the current buffer with data from the received frame.

CFR

: Correctly Frame Received

A receive frame is ended with a correct CRC. The end of the frame is located in the last descriptor

if several Descriptors.

IX.5 - Receive Command / Indicate Interrupt

IX.5.1 - Receive Command / Indicate Interrupt when TSV = 0

Time Stamping not validated (bit of GCR Register)

bit15

bit8

bit7

bit 0

C6/A

C5/E C4/S1 C3/S2 C2/S3 C1/S4

This word is located in the Command/Indicate interrupt queue ; IQSR Register indicates the size of this

interrupt queue located in the external memory.

: New Status.

Before writing the features of event in the external memory the Interrupt Controller reads the

NS bit :

if NS = 0, the Interrupt Controller puts this bit at ‘1’ when it writes the new primitive which has

been received.

if NS = 1, the Interrupt Controller puts INTFOV bit at ‘1’ to generate an interrupt (IR Interrupt

When the microprocessor has read the status word, it puts this bit at ‘0’ to acknowledge the new

status. This location becomes free for the Interrupt Controller.

S0/S1 Source of the event:

Word stored in shared memory

Primitive C1/6 received from GCI Multiplex 0 corresponding to DIN4

Primitive C1/6 received from GCI Multiplex 1 corresponding to DIN5

A, E, S1/S4 bits from any input timeslot switched to one timeslot 4n+3 of GCI 0 without

outgoing to DOUT4

A, E, S1/S4 bits from any input timeslot switched to one timeslot 4n+3 of GCI 1 without

outgoing to DOUT5

AIS detected during more 30 ms from any input timeslot and switched to B1, B2

channels (16 bits) of the GCI 0 (DOUT4) in transparent mode or not

AIS detected during more 30 ms from any input timeslot and switched to B1, B2

channels (16 bits) of the GCI 1 (DOUT5) in transparent mode or not.

Reserved

IX - EXTERNAL REGISTERS (continued)

STLC5465B

97/101

STLC5465B Arkusz danych(PDF) 97 Page - STMicroelectronics

STLC5465B Arkusz danych(HTML) 97 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Arkusz danych Pobierz

Link URL