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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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STLC5465B Arkusz danych(PDF) 46 Page - STMicroelectronics |
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STLC5465B Arkusz danych(HTML) 46 Page - STMicroelectronics |
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46 / 101 page  V - CLOCK TIMING (continued) V.2 - TDM Synchronization Symbol Parameter Min. Typ. Max. Unit t1 DCLK Clock Period if 4096kHz (3072) DCLK Clock Period if 2048kHz (1536) Id CLOCKA or B 244 (325) 488 (651) Id CLOCKA or B ns ns t2 Delay between CLOCK A or B and DCLK (30pF) V DD =5V V DD = 3.3V 5 20 30 32 ns ns t3 Set-up Time FS/DCLK 20 t1-20 ns t4 Hold Time FS/DCLK 20 ns t5 Duration FS 244 (325) 125000-244 ns t6 DCLK to Data 50pF DCLK to Data 100pF 50 100 ns t7 Set-up Time Data/DCLK 20 ns t7 Hold Time Data/DCLK 20 ns t8 Set-up Echo/DCLK (rising edge) 155 ns t9 Hold Time Echo/DCLK (rising edge) 205 ns t1 t3 Bit0,TimeSlot0 t7 t7 DCLK delivered by the Multi-HDLC FS delivered by the Multi-HDLC DOUT0/7, CB DIN0/8 The four Multiplex Configuration Registers are at zero (no delay between FS and Multiplexes). t8 CLOCK A (or B) t4 t2 t5 Bit 7, Time Slot 31 ECHO t9 t6 Figure 35 : Synchronization Signals received by the Multi-HDLC STLC5465B 46/101 |
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