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MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 0

Electrical Characteristics

Freescale Semiconductor

The UPM machine and GPCM machine outputs change on the internal tick selected by the memory controller configuration.

The AC timing specifications are relative to the internal tick. SDRAM machine outputs change only on the REFCLK rising edge.

Table 14. AC Timing for SIU Inputs

No.

Characteristic

Ref = CLKIN at 1.1 V

and 100 MHz

Units

Hold time for all signals after the 50% level of the REFCLK rising edge

0.5

11a

ARTRY/ABB set-up time before the 50% level of the REFCLK rising edge

3.1

11b

DBG/DBB/BG/BR/TC set-up time before the 50% level of the REFCLK rising

edge

3.6

11c

AACK set-up time before the 50% level of the REFCLK rising edge

3.0

11d

TA/TEA/PSDVAL set-up time before the 50% level of the REFCLK rising edge

•

Data-pipeline mode

•

Non-pipeline mode

3.5

4.4

Data bus set-up time before REFCLK rising edge in Normal mode

•

Data-pipeline mode

•

Non-pipeline mode

1.9

4.2

131

Data bus set-up time before the 50% level of the REFCLK rising edge in ECC

and PARITY modes

•

Data-pipeline mode

•

Non-pipeline mode

2.0

8.2

141

DP set-up time before the 50% level of the REFCLK rising edge

•

Data-pipeline mode

•

Non-pipeline mode

2.0

7.9

15a

TS and Address bus set-up time before the 50% level of the REFCLK rising edge

•

Extra cycle mode (SIUBCR[EXDD] = 0)

•

No extra cycle mode (SIUBCR[EXDD] = 1)

4.2

5.5

15b

Address attributes: TT/TBST/TSZ/GBL set-up time before the 50% level of the

REFCLK rising edge

•

Extra cycle mode (SIUBCR[EXDD] = 0)

•

No extra cycle mode (SIUBCR[EXDD] = 1)

3.7

4.8

PUPMWAIT signal set-up time before the 50% level of the REFCLK rising edge

3.7

IRQx setup time before the 50% level; of the REFCLK rising edge3

4.0

IRQx minimum pulse width3

6.0 + TREFCLK

Notes:

Timings specifications 13 and 14 in non-pipeline mode are more restrictive than MSC8102 timings.

Values are measured from the 50% TTL transition level relative to the 50% level of the REFCLK rising edge.

Guaranteed by design.

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