MSC8112 datasheet(34/44 Pages) FREESCALE

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MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semiconductor

2.5.10.4

SMII Mode

2.5.11

GPIO Timing

Table 27. SMII Mode Signal Timing

No.

Characteristics

Min

Max

Unit

808

ETHSYNC_IN, ETHRXD to ETHCLOCK rising edge set-up time

1.0

—

809

ETHCLOCK rising edge to ETHSYNC_IN, ETHRXD hold time

1.0

—

810

ETHCLOCK rising edge to ETHSYNC, ETHTXD output delay

1.51

6.02

Notes:

Measured using a 5 pF load.

Measured using a 15 pF load.

Figure 26. SMII Mode Signal Timing

Table 28. GPIO Timing

No.

Characteristics

Ref = CLKIN

Unit

Min

Max

601

REFCLK edge to GPIO out valid (GPIO out delay time)

—

6.1

602

REFCLK edge to GPIO out not valid (GPIO out hold time)

1.1

—

603

REFCLK edge to high impedance on GPIO out

—

5.4

604

GPIO in valid to REFCLK edge (GPIO in set-up time)

3.5

—

605

REFCLK edge to GPIO in not valid (GPIO in hold time)

0.5

—

Figure 27. GPIO Timing

Valid

ETHCLOCK

ETHSYNC_IN

ETHRXD

ETHSYNC

ETHTXD

Valid

810

809

808

REFCLK

GPIO

(Output)

GPIO

(Input)

Valid

603

High Impedance

604

605

602

601

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