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MSC8112 Arkusz danych(PDF) 31 Page - Freescale Semiconductor, Inc |
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MSC8112 Arkusz danych(HTML) 31 Page - Freescale Semiconductor, Inc |
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31 / 44 page ![]() MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor 31 2.5.8 UART Timing 2.5.9 Timer Timing Table 22. UART Timing No. Characteristics Expression Min Max Un it 400 URXD and UTXD inputs high/low duration 16 × TREFCLK 160.0 — ns 401 URXD and UTXD inputs rise/fall time 10 ns 402 UTXD output rise/fall time 10 ns Figure 20. UART Input Timing Figure 21. UART Output Timing Table 23. Timer Timing No. Characteristics Ref = CLKIN Unit Min Max 500 TIMERx frequency 10.0 — ns 501 TIMERx Input high period 4.0 — ns 502 TIMERx Output low period 4.0 — ns 503 TIMERx Propagations delay from its clock input 3.1 9.5 ns Figure 22. Timer Timing UTXD, URXD 400 inputs 400 401 401 UTXD output 402 402 500 502 501 TIMERx (Input) TIMERx (Output) 503 |
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