MSC8112 datasheet(39/44 Pages) FREESCALE

39 / 44 page

Hardware Design Considerations

MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semiconductor

•

HDST

can be disconnected if the DSI is in big-endian mode, or if the DSI is in little-endian mode and the

DCR[DSRFA] bit is set.

•

When the DSI is in 64-bit data bus mode and DCR[BEM] is cleared, pull up HWBS[1–3]/HDBS[1–3]/HWBE[1–3]/

HDBE[1–3]

and HWBS[4–7]/HDBS[4–7]/HWBE[4–7]/HDBE[4–7]/PWE[4–7]/PSDDQM[4–7]/PBS[4–7].

•

When the DSI is in 32-bit data bus mode and DCR[BEM] is cleared, HWBS[1–3]/HDBS[1–3]/HWBE[1–3]/HDBE[1–3]

must be pulled up.

•

When the DSI is in asynchronous mode, HBRST and HCLKIN should either be disconnected or pulled up.

•

When the DSI uses sliding window address mode (DCR[SLDWA] = 1), the external HA[11–13] signals must be

connected (tied) to the correct voltage levels so that the host can perform the first access to the DCR. After reset, the

DSI expects full address mode (DCR[SLDWA] = 0). The DCR address in the DSI memory map is 0x1BE000, which

requires the following connections:

— HA11 must be pulled high (1)

— HA12 must be pulled high (1)

— HA13 must be pulled low (0)

•

The following signals must be pulled up: HRESET, SRESET, ARTRY, TA, TEA, PSDVAL, and AACK.

•

In single-master mode (BCR[EBM] = 0) with internal arbitration (PPC_ACR[EARB] = 0):

— BG, DBG, and TS can be left unconnected.

— EXT_BG[2–3], EXT_DBG[2–3], and GBL can be left unconnected if they are multiplexed to the system bus

functionality. For any other functionality, connect the signal lines based on the multiplexed functionality.

— BR must be pulled up.

— EXT_BR[2–3] must be pulled up if multiplexed to the system bus functionality.

•

If there is an external bus master (BCR[EBM] = 1):

— BR, BG, DBG, and TS must be pulled up.

— EXT_BR[2–3], EXT_BG[2–3], and EXT_DBG[2–3] must be pulled up if multiplexed to the system bus

functionality.

•

In single-master mode, ABB and DBB can be selected as IRQ inputs and be connected to the non-active value. In other

modes, they must be pulled up.

Note:

The MSC8112 does not support DLL-enabled mode. For the following two clock schemes, ensure that the DLL is

disabled (that is, the DLLDIS bit in the Hard Reset Configuration Word is set).

•

If no system synchronization is required (for example, the design does not use SDRAM), you can use any of the

available clock modes.

•In the CLKIN synchronization mode, use the following connections:

— Connect the oscillator output through a buffer to CLKIN.

— Connect the CLKIN buffer output to the slave device (for example, SDRAM) making sure that the delay path

between the clock buffer to the MSC8112 and the SDRAM is equal (that is, has a skew less than 100 ps).

— Valid clock modes in this scheme are: 0, 7, 15, 19, 21, 23, 28, 29, 30, and 31.

Note:

See the Clock chapter in the MSC8113 Reference Manual for details.

•

If the 60x-compatible system bus is not used and SIUMCR[PBSE] is set, PPBS can be disconnected. Otherwise, it

should be pulled up.

•

The following signals: SWTE, DSISYNC, DSI64, MODCK[1–2], CNFGS, CHIPID[0–3], RSTCONF and BM[0–2] are

used to configure the MSC8112 and are sampled on the deassertion of the PORESET signal. Therefore, they should

be tied to GND or VDDH or through a pull-down or a pull-up resistor until the deassertion of the PORESET signal.

•

When they are used, INT_OUT (if SIUMCR[INTODC] is cleared), NMI_OUT, and IRQxx (if not full drive) signals must

be pulled up.

•

When the Ethernet controller is enabled and the SMII mode is selected, GPIO10 and GPIO14 must not be connected

externally to any signal line.

Note:

For details on configuration, see the MSC8112 User’s Guide and MSC8112 Reference Manual. For additional

information, refer to the MSC8113 Design Checklist (ANxxxx).

MSC8112 Arkusz danych(PDF) 39 Page - Freescale Semiconductor, Inc

MSC8112 Arkusz danych(HTML) 39 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Arkusz danych Pobierz

Link URL