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MSC8112 Arkusz danych(PDF) 15 Page - Freescale Semiconductor, Inc |
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MSC8112 Arkusz danych(HTML) 15 Page - Freescale Semiconductor, Inc |
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15 / 44 page ![]() Electrical Characteristics MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor 15 Table 5. DC Electrical Characteristics Characteristic Symbol Min Typical Max Unit Input high voltage1, all inputs except CLKIN VIH 2.0 — 3.465 V Input low voltage1 VIL GND 0 0.8 V CLKIN input high voltage VIHC 2.4 3.0 3.465 V CLKIN input low voltage VILC GND 0 0.8 V Input leakage current, VIN = VDDH IIN –1.0 0.09 1 µA Tri-state (high impedance off state) leakage current, VIN = VDDH IOZ –1.0 0.09 1 µA Signal low input current, VIL = 0.8 V 2 IL –1.0 0.09 1 µA Signal high input current, VIH = 2.0 V 2 IH –1.0 0.09 1 µA Output high voltage, IOH = –2 mA, except open drain pins VOH 2.0 3.0 — V Output low voltage, IOL= 3.2 mA VOL —0 0.4 V VCCSYN PLL supply current IVCCSYN —2 4 mA Internal supply current: • Wait mode • Stop mode IDDW IDDS — — 3753 2903 — — mA mA Typical power 300 MHz at 1.1 V4 P— 554 — mW Notes: 1. See Figure 5 for undershoot and overshoot voltages. 2. Not tested. Guaranteed by design. 3. Measured for 1.1 V core at 25°C junction temperature. 4. The typical power values were calculated using a power calculator configured for two cores performing an EFR code with the device running at the specified operating frequency and a junction temperature of 25°C. No peripherals were included. The calculator was created using CodeWarrior® 2.5. These values are provided as examples only. Power consumption is application dependent and varies widely. To assure proper board design with regard to thermal dissipation and maintaining proper operating temperatures, evaluate power consumption for your application and use the design guidelines in Chapter 4 of this document and in MSC8102, MSC8122, and MSC8126 Thermal Management Design Guidelines (AN2601). Figure 5. Overshoot/Undershoot Voltage for VIH and VIL GND GND – 0.3 V GND – 0.7 V VIL VIH Must not exceed 10% of clock period VDDH + 17% VDDH + 8% VDDH |
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