RA4M1 datasheet(67/131 Pages) RENESAS

67 / 131 page

R01DS0355EJ0110 Rev.1.10

Page 67 of 131

Sep 29, 2023

RA4M1 Group

2. Electrical Characteristics

2.3.6

I/O Ports, POEG, GPT, AGT, KINT, and ADC14 Trigger Timing

Note 1.

Constraints on input cycle:

When not switching the source clock: tPcyc × 2 < tACYC should be satisfied.

When switching the source clock: tPcyc × 6 < tACYC should be satisfied.

Note:

tPcyc: PCLKB cycle, tPDcyc: PCLKD cycle

Figure 2.38

I/O ports input timing

Figure 2.39

POEG input trigger timing

Table 2.31

I/O Ports, POEG, GPT, AGT, KINT, and ADC14 trigger timing

Parameter

Symbol Min

Max

Unit

Test

conditions

I/O ports

Input data pulse width

tPRW

1.5

tPcyc

Figure 2.38

Input/output data cycle (P002, P003, P004, P007)

tPOcyc

POEG

POEG input trigger pulse width

tPOEW

tPcyc

Figure 2.39

GPT

Input capture pulse width

Single edge

tGTICW

1.5

tPDcyc

Figure 2.40

Dual edge

2.5

AGT

AGTIO, AGTEE input cycle

2.7 V ≤ VCC ≤ 5.5 V

tACYC*1 250

Figure 2.41

2.4 V ≤ VCC < 2.7 V

500

1.8 V ≤ VCC < 2.4 V

1000

1.6 V ≤ VCC < 1.8 V

2000

AGTIO, AGTEE input high level

width, low-level width

2.7 V ≤ VCC ≤ 5.5 V

tACKWH,

tACKWL

100

2.4 V ≤ VCC < 2.7 V

200

1.8 V ≤ VCC < 2.4 V

400

1.6 V ≤ VCC < 1.8 V

800

AGTIO, AGTO, AGTOA, AGTOB

output cycle

2.7 V ≤ VCC ≤ 5.5 V

tACYC2

62.5

Figure 2.41

2.4 V ≤ VCC < 2.7 V

125

1.8 V ≤ VCC < 2.4 V

250

1.6 V ≤ VCC < 1.8 V

500

ADC14

14-bit A/D converter trigger input pulse width

tTRGW

1.5

tPcyc

Figure 2.42

KINT

KRn (n = 00 to 07) pulse width

tKR

250

Figure 2.43

Port

tPRW

POEG input trigger

tPOEW

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