RA4M1 datasheet(69/131 Pages) RENESAS

69 / 131 page

R01DS0355EJ0110 Rev.1.10

Page 69 of 131

Sep 29, 2023

RA4M1 Group

2. Electrical Characteristics

Note 1.

tPBcyc: PCLKB cycle.

Note 2.

tcac: CAC count clock source cycle.

2.3.8

SCI Timing

Note 1.

tPcyc: PCLKA cycle.

Figure 2.44

SCK clock input timing

Table 2.33

SCI timing (1)

Parameter

Symbol

Min

Max

Unit*1

Test

conditions

SCI

Input clock cycle

Asynchronous

tScyc

tPcyc

Figure 2.44

Clock synchronous

Input clock pulse width

tSCKW

0.4

0.6

tScyc

Input clock rise time

tSCKr

-20

Input clock fall time

tSCKf

-20

Output clock cycle

Asynchronous

tScyc

tPcyc

Clock synchronous

Output clock pulse width

tSCKW

0.4

0.6

tScyc

Output clock rise time

1.8 V or above

tSCKr

-20

1.6 V or above

Output clock fall time

1.8 V or above

tSCKf

-20

1.6 V or above

Transmit data delay

(master)

Clock

synchronous

1.8 V or above

tTXD

-40

Figure 2.45

1.6 V or above

Transmit data delay

(slave)

Clock

synchronous

2.7 V or above

2.4 V or above

1.8 V or above

100

1.6 V or above

125

Receive data setup

time (master)

Clock

synchronous

2.7 V or above

tRXS

2.4 V or above

1.8 V or above

1.6 V or above

110

Receive data setup

time (slave)

Clock

synchronous

2.7 V or above

1.6 V or above

Receive data hold

time (master)

Clock synchronous

tRXH

Receive data hold

time (slave)

Clock synchronous

tRXH

tSCKW

tSCKr

tSCKf

tScyc

SCKn

(n = 0 to 2, 9)

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