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RA4M1 Arkusz danych(PDF) 8 Page - Renesas Technology Corp |
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RA4M1 Arkusz danych(HTML) 8 Page - Renesas Technology Corp |
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8 / 131 page ![]() R01DS0355EJ0110 Rev.1.10 Page 8 of 131 Sep 29, 2023 RA4M1 Group 1. Overview 1.2 Block Diagram Figure 1.1 shows a block diagram of the MCU superset. Some individual devices within the group have a subset of the features. Figure 1.1 Block diagram Memory 256 KB Code Flash 8 KB Data Flash 32 KB SRAM DMA DMAC × 4 System Mode Control Power Control ICU MOSC/SOSC Clocks (HOCO/ MOCO/ LOCO) PLL Battery Backup GPT32 × 2 Timers AGT × 2 RTC CTSU Arm Cortex-M4 DSP FPU MPU NVIC System Timer Test and DBG Interface Bus MPU DTC WDT/IWDT CAC POR/LVD Reset Human machine interfaces SLCDC ELC Event Link SCE5 Security Analog CRC Data processing DOC Communication interfaces IIC × 2 SPI × 2 CAN × 1 SSIE × 1 USBFS with Battery Charging revision 1.2 SCI × 4 TSN DAC12 ACMPLP × 2 ADC14 OPAMP × 4 GPT16 × 6 DAC8 KINT Register Write Protection |
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