RA4M1 datasheet(73/131 Pages) RENESAS

73 / 131 page

R01DS0355EJ0110 Rev.1.10

Page 73 of 131

Sep 29, 2023

RA4M1 Group

2. Electrical Characteristics

Figure 2.50

SCI simple SPI mode timing for slave when CKPH = 0

Note 1.

tIICcyc: Clock cycle selected by the SMR.CKS[1:0] bits.

Note 2.

Cb indicates the total capacity of the bus line.

Table 2.35

SCI timing (3)

Conditions: VCC = 2.7 to 5.5 V

Parameter

Symbol

Min

Max

Unit

Test conditions

Simple I2C

(Standard mode)

SDA input rise time

tSr

1000

Figure 2.51

SDA input fall time

tSf

300

SDA input spike pulse removal time

tSP

04 × tIICcyc*1

Data input setup time

tSDAS

250

Data input hold time

tSDAH

SCL, SDA capacitive load

Cb*2

400

Simple I2C

(Fast mode)

SDA input rise time

tSr

300

Figure 2.51

For all ports

except P408, use

PmnPFS.DSCR

of middle drive.

For port P408,

use

PmnPFS.DSCR1

/DSCR of middle

drive for IIC

fast-mode.

SDA input fall time

tSf

300

SDA input spike pulse removal time

tSP

04 × tIICcyc*1

Data input setup time

tSDAS

100

Data input hold time

tSDAH

SCL, SDA capacitive load

Cb*1

400

tDr, tDf

tSA

tOH

tLEAD

tTD

tLAG

LSB OUT

(Last data)

DATA

MSB OUT

MSB IN

DATA

LSB IN

MSB IN

LSB OUT

tSU

tOD

tREL

MSB OUT

SSn

input

SCKn

CKPOL = 1

input

SCKn

CKPOL = 0

input

MISOn

output

MOSIn

input

(n = 0 to 2, 9)

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