RA4M1 datasheet(75/131 Pages) RENESAS

75 / 131 page

R01DS0355EJ0110 Rev.1.10

Page 75 of 131

Sep 29, 2023

RA4M1 Group

2. Electrical Characteristics

2.3.9

SPI Timing

Table 2.36

SPI timing (1 of 2)

Conditions: Middle drive output is selected in the Port Drive Capability bit in PmnPFS register

Parameter

Symbol

Min

Max

Unit*1

Test conditions

SPI

RSPCK clock cycle

Master

tSPcyc

2*4

4096

tPcyc

Figure 2.52

Slave

4096

RSPCK clock high

pulse width

Master

tSPCKWH

(tSPcyc -

tSPCKr-

tSPCKf) / 2 -

-ns

Slave

3 × tPcyc

RSPCK clock low

pulse width

Master

tSPCKWL

(tSPcyc -

tSPCKr -

tSPCKf) / 2 -

-ns

Slave

3 × tPcyc

RSPCK clock rise

and fall time

Output

2.7 V or above

tSPCKr,

tSPCKf

-10

2.4 V or above

1.8 V or above

1.6 V or above

Input

µs

Data input setup time Master

tSU

Figure 2.53 to

Figure 2.58

Slave

2.4 V or above

1.8 V or above

1.6 V or above

Data input hold time

Master

(RSPCK is PCLKA/2)

tHF

Master

(RSPCK is other than

above.)

tPcyc

Slave

SSL setup time

Master

1.8 V or above

tLEAD

-30 + N ×

tSpcyc*2

-ns

1.6 V or above

-50 + N ×

tSpcyc*2

Slave

6 × tPcyc

SSL hold time

Master

tLAG

-30 + N ×

tSpcyc*3

Slave

6 × tPcyc

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