RA4M1 datasheet(70/131 Pages) RENESAS

70 / 131 page

R01DS0355EJ0110 Rev.1.10

Page 70 of 131

Sep 29, 2023

RA4M1 Group

2. Electrical Characteristics

Figure 2.45

SCI input/output timing in clock synchronous mode

Table 2.34

SCI timing (2) (1 of 2)

Parameter

Symbol

Min

Max

Unit

Test conditions

Simple

SPI

SCK clock cycle output (master)

tSPcyc

65,536

tPcyc

Figure 2.46

SCK clock cycle input (slave)

65,536

SCK clock high pulse width

tSPCKWH

0.4

0.6

tSPcyc

SCK clock low pulse width

tSPCKWL

0.4

0.6

tSPcyc

SCK clock rise and fall time

1.8 V or above

tSPCKr,

tSPCKf

-20

1.6 V or above

Data input setup

time

Master

2.7 V or above

tSU

Figure 2.47 to

Figure 2.50

2.4 V or above

1.8 V or above

1.6 V or above

110

Slave

2.7 V or above

1.6 V or above

Data input hold time Master

33.3

Slave

SS input setup time

tLEAD

tSPcyc

SS input hold time

tLAG

tSPcyc

Data output delay

Master

1.8 V or above

tOD

-40

1.6 V or above

Slave

2.4 V or above

1.8 V or above

100

1.6 V or above

125

Data output hold

time

Master

2.7 V or above

tOH

-10

2.4 V or above

-20

1.8 V or above

-30

1.6 V or above

-40

Slave

-10

Data rise and fall

time

Master

1.8 V or above

tDr, tDf

-20

1.6 V or above

Slave

1.8 V or above

1.6 V or above

tTXD

tRXS tRXH

TXDn

RXDn

SCKn

(n = 0 to 2, 9)

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