RA4M1 datasheet(84/131 Pages) RENESAS

84 / 131 page

R01DS0355EJ0110 Rev.1.10

Page 84 of 131

Sep 29, 2023

RA4M1 Group

2. Electrical Characteristics

Figure 2.63

SSIE data output delay from SSILRCK0/SSIFS0 change time

2.3.12

CLKOUT Timing

Note 1.

When the EXTAL external clock input or an oscillator is used with division by 1 (the CKOCR.CKOSEL[2:0] bits are 011b and

the CKOCR.CKODIV[2:0] bits are 000b) to output from CLKOUT, the above should be satisfied with an input duty cycle of 45 to

55%.

Note 2.

When the MOCO is selected as the clock output source (the CKOCR.CKOSEL[2:0] bits are 001b), set the clock output division

ratio selection to be divided by 2 (the CKOCR.CKODIV[2:0] bits are 001b).

Figure 2.64

CLKOUT output timing

Table 2.39

CLKOUT timing

Parameter

Symbol

Min

Max

Unit*1

Test conditions

CLKOUT

CLKOUT pin output cycle*1

VCC = 2.7 V or above

tCcyc

62.5

Figure 2.64

VCC = 1.8 V or above

125

VCC = 1.6 V or above

250

CLKOUT pin high pulse width*2

VCC = 2.7 V or above

tCH

VCC = 1.8 V or above

VCC = 1.6 V or above

150

CLKOUT pin low pulse width*2

VCC = 2.7 V or above

tCL

VCC = 1.8 V or above

VCC = 1.6 V or above

150

CLKOUT pin output rise time

VCC = 2.7 V or above

tCr

-12

VCC = 1.8 V or above

VCC = 1.6 V or above

CLKOUT pin output fall time

VCC = 2.7 V or above

tCf

-12

VCC = 1.8 V or above

VCC = 1.6 V or above

tDTRW

SSILRCK0/SSIFS0

(Input)

SSITXD0 (Output)

MSB bit output delay from SSILRCK0/SSIFS0 change time for

slave transmitter when DEL = 1, SDTA = 0 or DEL = 1, SDTA = 1, SWL[2:0] = DWL[2:0]

tCf

tCH

tCcyc

tCr

tCL

CLKOUT pin output

Test conditions: VOH = VCC × 0.7, VOL = VCC × 0.3, IOH = -1.0 mA, IOL = 1.0 mA, C = 30 pF

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