ATmega165 datasheet(87/336 Pages) ATMEL

87 / 336 page

ATmega165/V

2573G–AVR–07/09

Table 45 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to

phase correct PWM mode.

Note:

1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case,

the compare match is ignored, but the set or clear is done at TOP. See “Phase Cor-

rect PWM Mode” on page 82 for more details.

• Bit 2:0 – CS02:0: Clock Select

The three Clock Select bits select the clock source to be used by the Timer/Counter.

If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will

clock the counter even if the pin is configured as an output. This feature allows software

control of the counting.

Timer/Counter Register –

TCNT0

The Timer/Counter Register gives direct access, both for read and write operations, to

the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes)

the compare match on the following timer clock. Modifying the counter (TCNT0) while

the counter is running, introduces a risk of missing a compare match between TCNT0

and the OCR0A Register.

Table 45. Compare Output Mode, Phase Correct PWM Mode

(1)

COM0A1

COM0A0

Description

Normal port operation, OC0A disconnected.

Reserved

Clear OC0A on compare match when up-counting. Set OC0A on

compare match when downcounting.

Set OC0A on compare match when up-counting. Clear OC0A on

compare match when downcounting.

Table 46. Clock Select Bit Description

CS02

CS01

CS00

Description

No clock source (Timer/Counter stopped)

001

clkI/O/(No prescaling)

010

clkI/O/8 (From prescaler)

011

clkI/O/64 (From prescaler)

100

clkI/O/256 (From prescaler)

101

clkI/O/1024 (From prescaler)

External clock source on T0 pin. Clock on falling edge.

External clock source on T0 pin. Clock on rising edge.

Bit

7654

321

TCNT0[7:0]

TCNT0

Read/Write

R/W

Initial Value

0000

000

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