ATmega165 datasheet(36/336 Pages) ATMEL

36 / 336 page

ATmega165/V

2573G–AVR–07/09

Brown-out Detector

If the Brown-out Detector is not needed by the application, this module should be turned

off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in

all sleep modes, and hence, always consume power. In the deeper sleep modes, this

will contribute significantly to the total current consumption. Refer to “Brown-out Detec-

tion” on page 40 for details on how to configure the Brown-out Detector.

Internal Voltage Reference

The Internal Voltage Reference will be enabled when needed by the Brown-out Detec-

tion, the Analog Comparator or the ADC. If these modules are disabled as described in

the sections above, the internal voltage reference will be disabled and it will not be con-

suming power. When turned on again, the user must allow the reference to start up

before the output is used. If the reference is kept on in sleep mode, the output can be

used immediately. Refer to “Internal Voltage Reference” on page 42 for details on the

start-up time.

Watchdog Timer

If the Watchdog Timer is not needed in the application, the module should be turned off.

If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence,

always consume power. In the deeper sleep modes, this will contribute significantly to

the total current consumption. Refer to “Watchdog Timer” on page 43 for details on how

to configure the Watchdog Timer.

Port Pins

When entering a sleep mode, all port pins should be configured to use minimum power.

The most important is then to ensure that no pins drive resistive loads. In sleep modes

where both the I/O clock (clk

I/O) and the ADC clock (clkADC) are stopped, the input buf-

fers of the device will be disabled. This ensures that no power is consumed by the input

logic when not needed. In some cases, the input logic is needed for detecting wake-up

conditions, and it will then be enabled. Refer to the section “Digital Input Enable and

Sleep Modes” on page 59 for details on which pins are enabled. If the input buffer is

enabled and the input signal is left floating or have an analog signal level close to V

CC/2,

the input buffer will use excessive power.

For analog input pins, the digital input buffer should be disabled at all times. An analog

signal level close to V

CC/2 on an input pin can cause significant current even in active

mode. Digital input buffers can be disabled by writing to the Digital Input Disable Regis-

ters (DIDR1 and DIDR0). Refer to “Digital Input Disable Register 1 – DIDR1” on page

188 and “Digital Input Disable Register 0 – DIDR0” on page 205 for details.

JTAG Interface and

On-chip Debug System

If the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power

down or Power save sleep mode, the main clock source remains enabled. In these

sleep modes, this will contribute significantly to the total current consumption. There are

three alternative ways to avoid this:

•

Disable OCDEN Fuse.

•

Disable JTAGEN Fuse.

•

Write one to the JTD bit in MCUCSR.

The TDO pin is left floating when the JTAG interface is enabled while the JTAG TAP

controller is not shifting data. If the hardware connected to the TDO pin does not pull up

the logic level, power consumption will increase. Note that the TDI pin for the next

device in the scan chain contains a pull-up that avoids this problem. Writing the JTD bit

in the MCUCSR register to one or leaving the JTAG fuse unprogrammed disables the

JTAG interface.

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