ATmega165 datasheet(34/336 Pages) ATMEL

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ATmega165/V

2573G–AVR–07/09

Oscillator is stopped during sleep. If the Timer/Counter2 is using the synchronous clock,

the clock source is stopped during sleep. Note that even if the synchronous clock is run-

ning in Power-save, this clock is only available for the Timer/Counter2.

Standby Mode

When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected,

the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to

Power-down with the exception that the Oscillator is kept running. From Standby mode,

the device wakes up in six clock cycles.

Notes:

1. Only recommended with external crystal or resonator selected as clock source.

2. If Timer/Counter2 is not running in asynchronous mode.

3. For INT0, only level interrupt.

Power Reduction

The Power Reduction Register, PRR, provides a method to stop the clock to individual

peripherals to reduce power consumption. The current state of the peripheral is frozen

and the I/O registers can not be read or written. Resources used by the peripheral when

stopping the clock will remain occupied, hence the peripheral should in most cases be

disabled before stopping the clock. Waking up a module, which is done by clearing the

bit in PRR, puts the module in the same state as before shutdown.

Module shutdown can be used in Idle mode and Active mode to significantly reduce the

overall power consumption. See “Supply Current of I/O modules” on page 290 for exam-

ples. In all other sleep modes, the clock is already stopped.

Power Reduction Register -

PRR

• Bit 7..4 - Res: Reserved bits

These bits are reserved in ATmega165 and will always read as zero.

• Bit 3 - PRTIM1: Power Reduction Timer/Counter1

Writing a logic one to this bit shuts down the Timer/Counter1 module. When the

Timer/Counter1 is enabled, operation will continue like before the shutdown.

Table 15. Active Clock Domains and Wake-up Sources in the Different Sleep Modes.

Active Clock Domains

Oscillators

Wake-up Sources

Sleep Mode

clk

CPU

clk

FLASH

clk

ADC

clk

ASY

Main Clock

Source

Enabled

Timer

Osc

Enabled

INT0

and Pin

Change

USI Start

Condition

Timer2

SPM/

EEPROM

Ready

ADC

Other

I/O

Idle

X(2)

ADC Noise

Reduction

X(2)

X(3)

XX(2)

Power-down

X(3)

Power-save

X(3)

Standby(1)

XX(3)

Bit

765

–

PRTIM1

PRSPI

PRUSART0

PRADC

PRR

Read/Write

R/W

Initial Value

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