ST7MC1K2 datasheet(52/371 Pages) STMICROELECTRONICS

52 / 371 page

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Supply, reset and clock management

ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto,

52/371

Application notes

The LVDRF flag is not cleared when another reset type occurs (external or watchdog), the

LVDRF flag remains set to keep trace of the original failure.

In this case, a watchdog reset can be detected by software while an external reset can not.

5AVDF

Voltage detector flag

This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt

request is generated when the AVDF bit changes value.

0: VDD over VIT+ (AVD) threshold

1: VDD under VIT-(AVD) threshold

4LVDRF

LVD reset flag

This bit indicates that the last reset was generated by the LVD block. It is set by

hardware (LVD reset) and cleared by software (writing zero). See WDGRF flag

description for more details. When the LVD is disabled by option byte, the LVDRF bit

value is undefined.

Reserved, must be kept cleared

CSSIE

Clock security system interrupt enable

This bit enables the interrupt when a disturbance is detected by the clock security

system (CSSD bit set). It is set and cleared by software.

0: Clock security system interrupt disabled

1: Clock security system interrupt enabled

When the PLL is disabled (PLLEN = 0), the CSSIE bit has no effect.

CSSD

Clock security system detection

This bit indicates a disturbance on the main clock signal (fOSC): The clock stops (at

least for a few cycles). It is set by hardware and cleared by reading the SICSR

0: Safe oscillator is not active

1: Safe oscillator has been activated

When the PLL is disabled (PLLEN = 0), the CSSD bit value must be kept cleared.

WDGRF

Watchdog reset flag

This bit indicates that the last reset was generated by the watchdog peripheral. It is

set by hardware (watchdog reset) and cleared by software (writing zero) or an LVD

reset (to ensure a stable cleared state of the WDGRF flag when CPU starts).

Combined with the LVDRF flag information, the flag description is given below:

00: Reset sources = external RESET pin

01: Reset sources = WDG

1X: Reset sources = LVD

Table 9.

SICSR (page 0) register description (continued)

Bit

Name

Function

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