ST7MC1K2 datasheet(87/371 Pages) STMICROELECTRONICS

87 / 371 page

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ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto

On-chip peripherals

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Figure 30.

Watchdog block diagram

The application program must write in the WDGCR register at regular intervals during

normal operation to prevent an MCU reset. This operation must occur only when the counter

value is lower than the window register value. The value to be stored in the WDGCR register

must be between FFh and C0h (see Figure 31).

Enabling the watchdog

When software watchdog is selected (by option byte), the watchdog is disabled after a reset.

It is enabled by setting the WDGA bit in the WDGCR register, then it cannot be disabled

again except by a reset.

When hardware watchdog is selected (by option byte), the watchdog is always active and

the WDGA bit is not used.

Controlling the downcounter

This downcounter is free-running and counts down even if the watchdog is disabled. When

the watchdog is enabled, the T6 bit must be set to prevent generating an immediate reset.

The T[5:0] bits contain the number of increments which represent the time delay before the

watchdog produces a reset (see Figure 31: Approximate timeout duration). The timing

varies between a minimum and a maximum value due to the unknown status of the

prescaler when writing to the WDGCR register (see Figure 32).

The window register (WDGWR) contains the high limit of the window: To prevent a reset, the

downcounter must be reloaded when its value is lower than the window register value and

greater than 3Fh. Figure 33 describes the window watchdog process.

Reset

WDGA

6-bit downcounter (CNT)

Watchdog control register (WDGCR)

Watchdog window register (WDGWR)

Comparator = 1

when T6:0 > W6:0

CMP

Write WDGCR

WDG prescaler Div 4

fOSC2

12-bit MCC

RTC counter

MSB

LSB

Div 64

MCC/RTC

TB[1:0] bits

(MCCSR

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